Lecture-06 - EEE 333: VHDL, L-06 Data Types Fall 2008, ASU...

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1 EEE 333: VHDL, L-06 EEE 333: VHDL, L-06 Fall 2008, ASU Yu (Kevin) Cao, yu.cao@asu.edu , GWC 336 Data Types Data Types EEE 333, ASU, Y. Cao Lecture 06 - 2 - Highlight Highlight ± VHDL syntax ± Data objects and types Signals, variables, and constants Scalar types Composite type ± Reading: Chapter 1, 2, 4 in Ashenden’s book ± Assignment: HW 02, due Oct. 9th
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2 EEE 333, ASU, Y. Cao Lecture 06 - 3 - Highlight Highlight ± VHDL syntax ± Data objects and types – Signals, variables, and constants – Scalar types – Composite type ± Reading: Chapter 1, 2, 4 in Ashenden’s book ± Assignment: HW 02, due Oct. 9th EEE 333, ASU, Y. Cao Lecture 06 - 4 - VHDL Simulation VHDL Simulation ± Analysis : Parse the codes for syntactic and semantic errors. Each unit is analyzed separately ± Elaboration : Flatten the design hierarchy to primitive components. Check the signals and processes ± Execution : Initialize the inputs. Simulate discrete events architecture struct of reg4 is signal int_clk: bit; begin bit0: entity work.d_latch(basic) port map (d0, int_clk, q0); bit1: entity work.d_latch(basic) port map (d1, int_clk, q1); bit2: entity work.d_latch(basic) port map (d2, int_clk, q2); bit3: entity work.d_latch(basic) port map (d3, int_clk, q3); gate: entity work.and2(basic) port map (en, clk, int_clk); end architecture struct;
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3 EEE 333, ASU, Y. Cao Lecture 06 - 5 - Identifiers: Naming Rules Identifiers: Naming Rules ± Rules: Only contain alphabetic characters, digits, and the underscore ‘ _ Must start with a letter May not end in an underscore May not have two consecutive underscores ± Valid identifier examples: A , counter , Next_Value , bit4 ± VHDL is not case sensitive, e.g., CAT = cat ± The underline is significant Example: Cat_1 is not Cat1 ! ± Exception: you can violate the rules with enclosing ‘ \ Example: \global.clk\ , \C:\\file\ EEE 333, ASU, Y. Cao Lecture 06 - 6 - Reserved Words, Symbols, Operators Reserved Words, Symbols, Operators ± They are special identifiers reserved by the system ± Examples: entity , architecture , and , or , in , out , etc. Follow the common sense as other languages
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Lecture-06 - EEE 333: VHDL, L-06 Data Types Fall 2008, ASU...

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