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HW 2 - solution

# HW 2 - solution - end process end only 2 Composite Types...

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EEE 333, ASU Fall 2008, Yu (Kevin) Cao Homework #2 1. Data Types: Chapter 2 in Ashenden’s book Exercises 1, 6, 7, 8 (1) constant number_of_bits:integer:=32; constant pi:real:=3.14159 (6) state'pos(standby) : 1 state'succ(active2) : error state'leftof(off) : error state'val(2) : active state'pred(active1) :standby state'right(off) : standby (7) 2*3 + 6/4 := 7 3+-4 := error “cat” & character'('0') :=cat0 true and x and not y or z := error B“101110” sll 3 :=110000 B“100010” sra 2) & X“2C” := “11_1000_0010_1100” (8) There can be several solutions to this however one of them is posted here: entity counter is port (clk : in bit; q : out integer); end; architecture only of counter is begin ctr: process(clk, reset) variable count:integer:=0; begin if clk'event and (clk = '1') then count:=count+1; q<=count; end if;

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Unformatted text preview: end process; end only; 2. Composite Types: Chapter 4 in Ashenden’s book Exercise 4 sub_type std_ulogic_vector is bits range 0 to 8; constant high_imp: std_ulogic_vector : = “zzzzzzzz”; 3. Modeling Constructs: Chapter 5 in Ashenden’s book Exercises 3, 4 (3)s'delayed(5ns) := Z at 5ns, ‘0’ at 15ns ‘1’ at 35ns H at 70ns Z at 105ns s'stable(5ns) := false at 0ns true at 5ns false at 10ns true at 15ns false at 30ns true at 35ns false at 65ns true at 70ns false at 100ns true at 105ns s'quiet(5ns) := false at 0ns true at 5ns false at 10ns true at 15ns false at 30ns true at 35ns false at 65ns true at 70ns false at 100ns true at 105ns s'transaction := 1 at 0ns 0 at 10ns 1 at 30ns 0 at 55ns 1 at 65ns 0 at 100ns s'last_event := 30ns s'last_active := 5ns s'last_value := 0 (4) wait on (S'event and S='1') until en='1';...
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HW 2 - solution - end process end only 2 Composite Types...

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