This preview has intentionally blurred sections. Sign up to view the full version.View Full Document
Unformatted text preview: end process; end only; 2. Composite Types: Chapter 4 in Ashenden’s book Exercise 4 sub_type std_ulogic_vector is bits range 0 to 8; constant high_imp: std_ulogic_vector : = “zzzzzzzz”; 3. Modeling Constructs: Chapter 5 in Ashenden’s book Exercises 3, 4 (3)s'delayed(5ns) := Z at 5ns, ‘0’ at 15ns ‘1’ at 35ns H at 70ns Z at 105ns s'stable(5ns) := false at 0ns true at 5ns false at 10ns true at 15ns false at 30ns true at 35ns false at 65ns true at 70ns false at 100ns true at 105ns s'quiet(5ns) := false at 0ns true at 5ns false at 10ns true at 15ns false at 30ns true at 35ns false at 65ns true at 70ns false at 100ns true at 105ns s'transaction := 1 at 0ns 0 at 10ns 1 at 30ns 0 at 55ns 1 at 65ns 0 at 100ns s'last_event := 30ns s'last_active := 5ns s'last_value := 0 (4) wait on (S'event and S='1') until en='1';...
View Full Document
- Spring '11
- Cao Homework, Ashenden, constant number_of_bits, standby state'right, error state'leftof, error state'val