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# HW 3 - EEE 333 ASU Fall 2008 Yu(Kevin Cao Homework#3 Due...

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EEE 333, ASU Fall 2008, Yu (Kevin) Cao Homework #3 Due Tuesday, October 28th, 1:30pm, submitted to me in class. The objective of homework 03 is to practice the VHDL coding of finite state machines. Please review related lectures and book chapters to start. You may use modelsim to check your answers. 1. VHDL Implementation Write the VHDL codes to implement the following Moore type FSM: F E1 E2 F = 0/ Stall = 1 Out = “111” IE2 = 1 or IE3 = 1/ Stall = 0 F = 1/ Stall = 0 On Reset = 1 all states go to F P E3 PF = 0/ Stall = 1 IE3 = 1/ Stall = 0 PF = 1/ Stall = 1 PF = 1/ Stall = 1 PF = 0/ Stall = 0 IE3 = 0/ Stall = 0 IE2 = 0 and IE3 = 0/ Stall = 0 PF = 1/ Stall = 1 Signals IE2 and IE3 are mutually excusive, PF cannot equal 1 in E1, E2 Any signal not mentioned on a transition is a don’t care input Out = “001” Out = “000” Out = “100” Out = “101” 2. State Transition Diagram Draw the state diagram of the following VHDL Moore type FSM, explicitly showing all don’t care conditions.

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HW 3 - EEE 333 ASU Fall 2008 Yu(Kevin Cao Homework#3 Due...

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