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ics6bwin11_11.3

# ics6bwin11_11.3 - 0H 11.3 Logic Gates 293 CTION 11.3 Logic...

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Unformatted text preview: 0H 11.3 Logic Gates 293 CTION 11.3 Logic Gates The inputs to the AND gate are T and 17. The output is then passed through the inverter. Therefore the ﬁnal output is (TT) Note that there is a simpler way to form a circuit equivalent to this one, 1121111er .1: —:— y. This is similar to the previous three exercises. The output is (T y Z)(T + y + E). ’6 build these circuits up exactly as the expressions are built up. In part (b) for example, we use an AND gate to join the outputs of the inverter (which was applied to the output of the OR gate applied to (1‘ and y) and :1“. (a) \/ (d) analog)“ to the situation with three switches in Example 3. we write down the expression we want the rcuit to implement: u: 41' 113+ “‘1‘ y .: : (1‘13 y: 2 nary: E 111.173]: 1 unity: 1 11,113] :~1~ 1121ng .:. The circuit will h 'e 32 inputs. combined by AND gates in groups of four. with inverters where necessary. to prtx'iuce outputs corresponding to the eight minternis in this expression. These outputs are combined with one big OR gate. he circuit is shown below, with the picture rotated for ease of display on the page. list we must determine what the outputs are to he. Let ‘1' and y be the input hits, where we want to mpute at w y. There are two outputs: the difference, hit 5 and the borrow bit I). The borrow will he 1 if a ‘ “ow is necessary. which happens only when 1‘ = 0 and y = 1. Thus I) = T 1/. The difference bit will he 1 bend? = 1 and y = 0, and when I = 0 and y = 1; and it will he 0 in the cases in which at = y. Therefore L have z = T y + .1737, which is the same as b + 17:17. Thus we can draw the half subtractor as shown below. analogy with Figure 8,. we represent the circuit with two inputs and two outputs. "CD Chapter 11 Boolean Algebra 'We need to combine half subtractors and full subtractors in much the same way that half adders and full adders were combined to produce a Circuit to add binary numbers. The ﬁrst bit of the answer (so) is the difference bit between the ﬁrst two bits of the input (.130 and go). obtained using the half subtractor. The borrow hit output from the half subtractor (I10) is then the borrow bit input to the full snbtractor for determining the second bit of the answer, and so on. Note that the ﬁnal borrow ()3 must be 0 and is not used. 7—3—>(no\ used) 14. Let (3383.9150b he the product. We need to write down Boolean expressions for each of these hits. Clearh s“ = 1:0 3/0. The bit 31 is a 1 if one. but not both. of the products 103/1 and Ill/0 are 1. Therefore we have .91 2 (1'0 111 + .1‘1 1/1))(«1’0 .r1 yo 1/1). A similar analysis. will show that 8;} = .r; yr (To + 170). and that 53 = .ru 1:1 in) y] . The circuit we want has one circuit for each of these hits. 16. The answers here are duals to the answers tori xercise 15 ..\‘ ote that the usual symbol .1 represents the NU]? operation. a) The (irtuit is the same as in Exercise 1)a.1 a N OR gate in place of a N —l \D gate since T .r ,1, .r . x ——{:‘i 13) Since .1: + .l/ = (,r 1,. y) l, (r j, y). the answer is as shown. \\ 34% X C) Since .ry 2: (.1? l .1?) l, (y 1, y). the answer is as shown. (1) “7e use the representation .r (y l y)) obtaining the follow ing circuit [0 w Ox i011 11,7l illinizuization of Circuits we know that the sum hit in the half adder is s = 1' 41:71} y : 1:17 «1— Ty. The answer to Exercise 16d shows L precisely this gate constructed from NOR gates, so it gives us this part of the answer. Also, the carry hit in the half adder is c : .ry. The answer to Exercise 1(5c shows precisely this gate constructed from NOR gates, _ so it gives us this part of the answer. a) The initial inputs have depth 0. Therefore the three AND gates all have, depth 1, as do their outputs. Therefore the OR gate has depth 2, which is the depth of the circuit. b) The AND gate at the top of Figure 6 and the two NOT gates have depth 1, so the AND gate at the bottom has depth ‘2. Therefore the inputs to the OR gate have depth 1 or ‘2, so its depth is 3 (one more than the maximum of these), which is the depth of the circuit. c) The maximum of the depths of the gates is 3, for the ﬁnal AND gate, since the NOT gate feeding it has depth ‘2. Therefore the depth of the circuit is 3. d) We have to be careful here, since the outputs of the half-adder are 3 for the sum but 1 for the carry. So the depth of the half adder at the top of this full at‘lder is 6 for its suin output and 4 for its carry output. The carry output goes through one more gate, giving a total depth of :3 for the OR gate, but the depth of the circuit is (5, because of the output at the upper right. ...
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ics6bwin11_11.3 - 0H 11.3 Logic Gates 293 CTION 11.3 Logic...

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