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Chapter 8
8.1. The expressions for the inputs of the FipFops are
D
2
=
Y
2
=
wy
2
+
y
1
y
2
D
1
=
Y
1
=
w
⊕
y
1
⊕
y
2
The output equation is
z
=
y
1
y
2
8.2. The excitation table for JK FipFops is
Present
±lipFop inputs
state
w
= 0
w
= 1
Output
y
2
y
1
J
2
K
2
J
1
K
1
J
2
K
2
J
1
K
1
z
00
1
d
0
d
1
d
1
d
0
01
0
d
d
0
0
d
d
1
0
10
d
0
1
d
d
1
0
d
0
11
d
0
d
1
d
1
d
0
1
The expressions for the inputs of the FipFops are
J
2
=
y
1
K
2
=
w
J
1
=
wy
2
+
w
y
2
K
1
=
J
1
The output equation is
z
=
y
1
y
2
8.3. A possible state table is
Present
Next state
Output
z
state
w
= 0
w
= 1
w
= 0
w
= 1
A
A
B
0
0
B
E
C
0
0
C
E
D
0
0
D
E
D
0
1
E
±
B
0
0
±
A
B
0
1
81
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View Full Document 8.4. Verilog code for the solution given in problem 8.3 is
module
prob8
4 (Clock, Resetn, w, z);
input
Clock, Resetn, w;
output
z;
reg
z;
reg
[3:1] y, Y;
parameter
[3:1] A = 3’b000, B = 3’b001, C = 3’b010, D = 3’b011, E = 3’b100, F = 3’b101;
// De±ne the next state and output combinational circuits
always
@(w or y)
case
(y)
A:
if
(w)
begin
Y = B;
z = 0;
end
else
begin
Y = A;
z = 0;
end
B:
if
(w)
begin
Y = C;
z = 0;
end
else
begin
Y = E;
z = 0;
end
C:
if
(w)
begin
Y = D;
z = 0;
end
else
begin
Y = E;
z = 0;
end
D:
if
(w)
begin
Y = D;
z = 1;
end
else
begin
Y = E;
z = 0;
end
E:
if
(w)
begin
Y = B;
z = 0;
end
else
begin
Y = F;
z = 0;
end
F:
if
(w)
begin
Y = B;
z = 1;
end
else
begin
Y = A;
z = 0;
end
default:
begin
Y = 3’bxxx;
z = 0;
end
endcase
82
// Defne the sequential block
always
@(
negedge
Resetn or
posedge
Clock)
if
(Resetn == 0)
y
<
= A;
else
y
<
= Y;
endmodule
8.5. A minimal state table is
Present
Next State
Output
state
w
= 0
w
= 1
z
A
A
B
0
B
E
C
0
C
D
C
0
D
A
F
1
E
A
F
0
F
E
C
1
8.6. An initial attempt at deriving a state table may be
Present
Next state
Output
z
state
w
= 0
w
= 1
w
= 0
w
= 1
A
A
B
0
0
B
D
C
0
0
C
D
C
1
0
D
A
E
0
1
E
D
C
0
0
States
B
and
E
are equivalent; hence the minimal state table is
Present
Next state
Output
z
state
w
= 0
w
= 1
w
= 0
w
= 1
A
A
B
0
0
B
D
C
0
0
C
D
C
1
0
D
A
B
0
1
83
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View Full Document 8.7. For Figure 8.51 have (using the straightforward state assignment):
Present
Next state
state
w
= 0
w
= 1
Output
y
3
y
2
y
1
Y
3
Y
2
Y
1
Y
3
Y
2
Y
1
z
A
0 0 0
0 0 1
0 1 0
1
B
0 0 1
0 1 1
1 0 1
1
C
0 1 0
1 0 1
1 0 0
0
D
0 1 1
0 0 1
1 1 0
1
E
1 0 0
1 0 1
0 1 0
0
F
1 0 1
1 0 0
0 1 1
0
G
1 1 0
1 0 1
1 1 0
0
This leads to
Y
3
=
wy
3
+
y
1
y
2
+
wy
1
y
3
Y
2
=
wy
3
+
w
y
1
y
2
+
wy
1
y
2
+
wy
1
y
2
y
3
Y
1
=
y
3
w
+
y
1
w
+
wy
1
y
2
z
=
y
1
y
3
+
y
2
y
3
For Figure 8.52 have
Present
Next state
state
w
= 0
w
= 1
Output
y
2
y
1
Y
2
Y
1
Y
2
Y
1
z
A
0 0
0 1
1 0
1
B
0 1
0 0
1 1
1
C
1 0
1 1
1 0
0
F
1 1
1 0
0 0
0
This leads to
Y
2
=
wy
2
+
y
1
y
2
+
w
y
2
Y
1
=
y
1
w
+
wy
1
y
2
z
=
y
2
Clearly, minimizing the number of states leads to a much simpler circuit.
84
8.8. For Figure 8.55 have (using straightforward state assignment):
Present
Next state
state
DN=00
01
10
11
Output
y
4
y
3
y
2
y
1
Y
4
Y
3
Y
2
Y
1
z
S1
0 0 0 0
0 0 0 0
0 0 1 0
0 0 0 1

0
S2
0 0 0 1
0 0 0 1
0 0 1 1
0 1 0 0

0
S3
0 0 1 0
0 0 1 0
0 1 0 1
0 1 1 0

0
S4
0 0 1 1
0 0 0 0



1
S5
0 1 0 0
0 0 1 0



1
S6
0 1 0 1
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This note was uploaded on 02/16/2011 for the course EE 4745 taught by Professor Rai during the Spring '07 term at LSU.
 Spring '07
 Rai

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