2-15-11 - The Basics of Exception Handling MIPS uses two...

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The Basics of Exception Handling MIPS uses two coprocessors : C0 and C1 for additional help. C0 primarily helps with exception handling , and C1 helps with floating point arithmetic. Each coprocessor has a few registers. Interrupts Initiated outside the instruction stream Arrive asynchronously (at no specific time), Example: o I/O device status change o I/O device error condition Traps Occur due to something in instruction stream. Examples: o Unaligned address error o Arithmetic overflow o System call
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MIPS coprocessor C0 has a cause register (Register 13) that contains a 4-bit code to identify the cause of an exception Cause register Bits 15-10 Bits 5-2 [Exception Code = 0 means I/O interrupt = 12 means arithmetic overflow etc] MIPS instructions that cause overflow (or some other violation) lead to an exception , which sets the exception code . It then switches to the kernel mode (designated by a bit in the status register of C0, register 12) and transfers control to a predefined address to invoke a
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This note was uploaded on 02/18/2011 for the course 22C 060 taught by Professor Ghosh during the Spring '11 term at University of Iowa.

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2-15-11 - The Basics of Exception Handling MIPS uses two...

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