2 - Illustration 3 • In a certain MOS process the Si0 2...

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Unformatted text preview: Illustration 3 • In a certain MOS process the Si0 2 gate dielectric of 750 A is specified. What is the maximum gate voltage the device can withstand before its breakdown? Assume the critical field for Si0 2 is 7 X 10 6 volts/em, and that the geometry is such that the E field is uniform. Assume that the oxide weakness factor is 2. Page 13 EMC Solution 3 • Since the oxide weakness factor is 2, the maximum field the dielectric can withstand is . 6 E rnax = 7 x 10 V / em 2 • The maximum voltage the gate can withstand is Vrnax = E rnax x dielectric separation 6 V rnax = 7x 10 x750x 10- 8 em 2 V rnax = 26.25 V • Therefore, the maximum voltage the gate can withstand is 26V. Page 14 Illustration 4 • Tw o metallic boxes containing electronic circuits are connected together by an interconnect cable. An EM event occurs at the surface of one of these boxes. To protect the other box from the external EM effects the cable is shielded. The best results would be under the following condition. (Make reasonable assumptions if necessary.) a) Each side of the shield not connected to connectors or boxes b) Each side of the shield soldered to connector 360 , and connector bulkhead in contact with the box with 4 screws c) Each side of the shield soldered to connector 360°, and I connector bonded to the box 360 • - ;-' i _ __ Page 15 j EMC Solution 4...
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This note was uploaded on 02/22/2011 for the course EE 529 taught by Professor Dr.j.j.whalen during the Fall '10 term at SUNY Buffalo.

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2 - Illustration 3 • In a certain MOS process the Si0 2...

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