HW1 - → MDR Read After the execution of all the...

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ECE 662 (Sp 2009) Homework 1 Solutions Problem 1 State Register transfer Control lines activated 0 [PC] MAR GPC2MAR 1 [[MAR]] M D R R e a d 2 [MDR] IR GMDR2IR 3 [PC] + 1 P C I N C P C 4 [AD] MAR GIR2MAR 5 [[MAR]] MDR Read 6 [MDR] X GMDR2X 7 [X]+[AC] AC ACin 8 [PC] MAR GPC2MAR 9 [[MAR]] M D R R e a d 10 [MDR] IR GMDR2IR 11 [PC] + 1 P C I N C P C 12 [AD] PC GIR2PC 13 [PC] MAR GPC2MAR 14 [[MAR]] MDR Read 15 [MDR] IR GMDR2IR 16 [PC] + 1 P C I N C P C 17 [AD] PC GIR2PC 18 [PC] MAR GPC2MAR 19 [[MAR]] MDR Read 20 [MDR] IR GMDR2IR 21 [PC] + 1 P C I N C P C 22 [AD] PC GIR2PC 22 [PC] MAR GPC2MAR 23 [[MAR]] MDR Read 24 [MDR] IR GMDR2IR 25 [PC] + 1 P C I N C P C 26 [AD] MAR GIR2MAR 27 [[MAR]] MDR Read 28 [MDR] MAR GMDR2MAR 29 [[MAR]]
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Unformatted text preview: → MDR Read After the execution of all the instructions, the content of AC is 20 ($14). Problem 2 State Register transfer Next State Fetch 0 [PC] → M A R 1 1 [[MAR]] → MDR 2 2 [MDR] → I R 3 3 [PC] + 1 → P C 4 4 [PC] → M A R 5 5 [[MAR]] → MDR 6 6 [PC] + 1 → PC 7, 11, 13 ADD address 7 [MDR] → M A R 8 8 [[MAR]] → MDR 9 9 [MDR] → X 1 10 [X]+[AC] → AC 0 ADD (address) 11 [MDR] → M A R 1 2 12 [[MAR]] → MDR 7 JMP address 13 [MDR] → P C Problem 3 a) No cache: Average execution time: 20T With cache: 0.96 x T +0.04 x (20T+T) = 1.8T Speed up factor: 20T/1.8T = 11.1 b) With cache: 0.98 x T +0.02 x (20T+T) = 1.4T Speed up factor: 20T/1.4T = 14.3...
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This note was uploaded on 02/21/2011 for the course ECE 662 taught by Professor Orin,d during the Winter '08 term at Ohio State.

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HW1 - → MDR Read After the execution of all the...

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