# HW5 - 18[MDR → Memory Write Inhibit if 0 if MFC=1 1 8 i f...

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1 ECE 662 (Sp 2009) Homework 5 (solutions) 1. Problem 7.16 of the textbook. 2. (a) Microinstructions State Register Transfer Control Lines Next State 0 [PC] MAR OPC, IMAR 1 1 [[MAR]] MDR Read, Inhibit if 2 if MFC=1 1 i f M F C = 0 2 [MDR] IR OMDR, IIR 3 3 [PC]+1 T2 OPC, IB, IT2, P1 4 4 [T2] PC OT2, IPC 14 if ADD(X) 5 o t h e r w i s e 5 [PC] MAR OPC, IMAR 6 6 [[MAR]] MDR Read, Inhibit if 15 if MFC=1 & JMP 7 i f M F C = 1 6 i f M F C = 0 7 [PC]+1 T2 OPC, IB, IT2, P1 8 8 [T2] PC OT2, IPC 16 if ST 9 otherwise 9 [MDR] MAR OMDR, IMAR 10 10 [[MAR]] MDR Read, Inhibit if 11 if MFC=1 & 1 9 i f M F C = 1 L D MFC JMP MFC LD MFC Run Inhibit MFC MFC Run, Write Run, Write

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2 1 0 i f M F C = 0 11 [MDR] T1 OMDR, IT1 12 12 [T1]+[AC] T2 IA, OAC, IB, IT2, IC, IV 13 13 [T2] AC OT2, IAC, IN, IZ 0 14 [X] MAR OX, IMAR 10 15 [MDR] PC OMDR, IPC 0 16 [MDR] MAR OMDR, IMAR 17 17 [AC] MDR OAC, IMDR, IN, IZ, CLRC, CLRV 18
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Unformatted text preview: 18 [MDR] → Memory Write, Inhibit if 0 if MFC=1 1 8 i f M F C = 19 [MDR] → AC OMDR, IN, IZ, CLRC, CLRV 0 (b) Implementation of the Control Signals and the counter inputs IPC = T2 + T8 + T15 OPC = T0 + T3 + T5 + T7 IMAR = T5 + T9 + T14 + T16 IMDR = T17 OMDR = T2 + T9 + T11 + T15 + T16 + T19 Read = T1 + T6 + T10 Write = T18 Inhibit = (T1 + T6 + T10 + T18) IIR = T2 IA = T12 IB = T3 + T7 + T12 P1 = T3 + T7 IT1 = T11 IT2 = T3 + T7 + T12 OT2 = T4 + T8 + T13 OX = T14 IAC = T13 + T19 OAC = T12 + T17 MFC MFC 3 IN = T13 + T17 + T19 IZ = T13 + T17 + T19 IV = T12 CLRV = T17 + T19 IC = T12 CLRC = T17 + T19 Preset = T4 . ADD(X) + T6 . JMP . MFC + T10 . LD . MFC + T13 + T14 + T15 + T18 . MFC + T19 D4 = T8 + T10 D3 = T4 + T6 + T14 D2 = T4 + T6 D1 = T4 + T6 + T10 + T14 D0 = T6 + T10...
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## This note was uploaded on 02/21/2011 for the course ECE 662 taught by Professor Orin,d during the Winter '08 term at Ohio State.

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HW5 - 18[MDR → Memory Write Inhibit if 0 if MFC=1 1 8 i f...

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