f37-book-intarch-pres-pt4

f37-book-intarch-pres-pt4 - Part IV Data Path and Control...

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Feb. 2009 Computer Architecture, Data Path and Control Slide 1 Part IV Data Path and Control
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Feb. 2009 Computer Architecture, Data Path and Control Slide 2 About This Presentation This presentation is intended to support the use of the textbook Computer Architecture: From Microprocessors to Supercomputers , Oxford University Press, 2005, ISBN 0-19-515455-X. It is updated regularly by the author as part of his teaching of the upper-division course ECE 154, Introduction to Computer Architecture, at the University of California, Santa Barbara. Instructors can use these slides freely in classroom teaching and for other educational purposes. Any other use is strictly prohibited. © Behrooz Parhami Edition Released Revised Revised Revised Revised First July 2003 July 2004 July 2005 Mar. 2006 Feb. 2007 Feb. 2008 Feb. 2009
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Feb. 2009 Computer Architecture, Data Path and Control Slide 3 A Few Words About Where We Are Headed Performance = 1 / Execution time simplified to 1 / CPU execution time CPU execution time = Instructions × CPI / (Clock rate) Performance = Clock rate / ( Instructions × CPI ) Define an instruction set; make it simple enough to require a small number of cycles and allow high clock rate, but not so simple that we need many instructions, even for very simple tasks (Chap 5-8) Design hardware for CPI = 1; seek improvements with CPI>1 (Chap 13-14) Design ALU for arithmetic & logic ops (Chap 9-12) Try to achieve CPI = 1 with clock that is as high as that for CPI > 1 designs; is CPI < 1 feasible? (Chap 15-16) Design memory & I/O structures to support ultrahigh-speed CPUs (chap 17-24)
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Feb. 2009 Computer Architecture, Data Path and Control Slide 4 IV Data Path and Control Topics in This Part Chapter 13 Instruction Execution Steps Chapter 14 Control Unit Synthesis Chapter 15 Pipelined Data Paths Chapter 16 Pipeline Performance Limits Design a simple computer (MicroMIPS) to learn about: • Data path – part of the CPU where data signals flow • Control unit – guides data signals through data path • Pipelining – a way of achieving greater performance
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Feb. 2009 Computer Architecture, Data Path and Control Slide 5 13 Instruction Execution Steps A simple computer executes instructions one at a time • Fetches an instruction from the loc pointed to by PC • Interprets and executes the instruction, then repeats Topics in This Chapter 13.1 A Small Set of Instructions 13.2 The Instruction Execution Unit 13.3 A Single-Cycle Data Path 13.4 Branching and Jumping 13.5 Deriving the Control Signals 13.6 Performance of the Single-Cycle Design
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Feb. 2009 Computer Architecture, Data Path and Control Slide 6 13.1 A Small Set of Instructions Fig. 13.1 MicroMIPS instruction formats and naming of the various fields. 5 bits 5 bits 31 25 20 15 0 Opcode Source 1 or base Source 2 or dest’n op rs rt R 6 bits 5 bits rd 5 bits sh 6 bits 10 5 fn jta Jump target address, 26 bits imm Operand / Offset, 16 bits Destination Unused Opcode ext I J inst Instruction, 32 bits Seven R-format ALU instructions ( add , sub , slt , and , or , xor , nor ) Six I-format ALU instructions ( lui , addi , slti , andi , ori , xori ) Two I-format memory access instructions ( lw , sw )
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This note was uploaded on 02/22/2011 for the course ECE 154 taught by Professor Staff during the Spring '08 term at UCSB.

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f37-book-intarch-pres-pt4 - Part IV Data Path and Control...

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