20 - VHDL - 22-Mar-0610:21 AM11University of Florida, EEL...

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Unformatted text preview: 22-Mar-0610:21 AM11University of Florida, EEL 3701 File 20 Dr. Eric M. SchwartzIntro to VHDLEEL 37011University of Florida, EEL 3701 File 20 Dr. Eric M. SchwartzEEL 3701Menu VHDL VHDL: The EntityVHL: IEEE 1076 TYPEVHDL: IEEE 1164 TYPEVHDL: The ArchitectureMixed-Logic in VHDLVHDL MUX examplesLook into my ...See examples on web-site: (VHDL Examples) NAnd2a.vhd,NAnd2b.vhd,Mux2to1*.vhd, * = a-f, Mux41*See also example file on web: Creating graphical components (Component_Creation.pdf)EEL 37012University of Florida, EEL 3701 File 20 Dr. Eric M. SchwartzEEL 3701Introduction to VHDL Q: What is VHDL? A: VHSICHardware Description Language Q: What is VHSIC? A: Very High Speed Integrated Circuits Q: What is VHDL used for? A: To describe and test a digital circuit in a high level language environment. When used in conjunction with a router and logic generator a silicon mask can be created. A competitor to VHDL is Verilog(older and more widely used until recently, but ...)22-Mar-0610:21 AM22University of Florida, EEL 3701 File 20 Dr. Eric M. SchwartzIntro to VHDLEEL 37013University of Florida, EEL 3701 File 20 Dr. Eric M. SchwartzEEL 3701VHDL Syntax VHDL is case insensitive>GOOD = Good= good = gOOD Everyone has there own conventions; mine follows:> Keyword of VHDL are all lower case> Entity and architecture names are all upper case> Identifiers start with a capital> All new words in a given identifier is again capitalized White space (spaces or tabs) is fine anywhere as separators The semicolon is a statement terminator Two dashes (--) indicate a comment follows Identifiers must begin with a letter; subsequent characters are alphanumeric or _ No precedence in VHDL; resolves left-to-right; useparen.(except nothas precedence over logical operators)EEL 37014University of Florida, EEL 3701 File 20 Dr. Eric M. SchwartzEEL 3701VHDL: The EntityentityNAND2a isport(A,B: in bit;C: out bit);end NAND2a; Example:Black BoxBlack BoxThe entity is the description of inputs and outputs The entity is the description of inputs and outputs to a black boxto a black boxentity BLACK_BOX is port(entity BLACK_BOX is port(Clock, Reset:Clock, Reset:ininbit;bit;D:D:ininbit_vector(7 bit_vector(7 downtodownto0);0);Q:Q:out bitout bit_vector(7 _vector(7 downtodownto0);0);CO:CO:out bit);out bit);end BLACK_BOX;end BLACK_BOX;22-Mar-0610:21 AM33University of Florida, EEL 3701 File 20 Dr. Eric M. SchwartzIntro to VHDLEEL 37015University of Florida, EEL 3701 File 20 Dr. Eric M. SchwartzEEL 3701VHDL: The EntityEntity syntax:entityNAND2a isport(A,B: in bit;C: out bit);end NAND2a;entity ENTITY_NAME is port(entity ENTITY_NAME is port(----optional parameterized componentsoptional parameterized componentsName1:Name1:modemodetype;type;Name2: Name2: modemodetype;type;NameNNameN: : modemodetype);type);end ENTITY_NAME;end ENTITY_NAME; Names can be a list of names separated by commas...
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This note was uploaded on 02/22/2011 for the course ECON 2023 taught by Professor Rush during the Spring '08 term at University of Florida.

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20 - VHDL - 22-Mar-0610:21 AM11University of Florida, EEL...

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