24 - GCPU_Comp Org_68HC11_Assembly

24 - GCPU_Comp Org_68HC11_Assembly - 6-Apr-064:12 PM GCPU,...

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6-Apr-06—4:12 PM 1 1 University of Florida, EEL 3701 – File 24 © Drs. Schwartz & Arroyo GCPU, Comp Org, 68HC11, Assembly EEL 3701 1 University of Florida, EEL 3701 – File 24 © Drs. Schwartz & Arroyo EEL 3701 Menu • Computer Organization • Programming Model for the an example microprocessors (the G-CPU & Motorola 68HC11) • Assembly Programming Look into my . .. See examples on web: DirAddr.asm, ExtAddr.asm, IndAddr.asm, ImmAddr.asm, Phone.asm EEL 3701 2 University of Florida, EEL 3701 – File 24 © Drs. Schwartz & Arroyo EEL 3701 Computer Functional Block Diagram DATA CONTROL CONTROL MEMORY I/O CPU ALU
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6-Apr-06—4:12 PM 2 2 University of Florida, EEL 3701 – File 24 © Drs. Schwartz & Arroyo GCPU, Comp Org, 68HC11, Assembly EEL 3701 3 University of Florida, EEL 3701 – File 24 © Drs. Schwartz & Arroyo EEL 3701 Memory and I/O Units Memory Unit Data Address MEMORY UNIT Data Out Read/Write Enable Data In Status I/O Unit INPUT/OUTPUT UNIT Device Address Control Data Out Data In Status Device Identity CONTROL MEMORY I/O CPU ALU EEL 3701 4 University of Florida, EEL 3701 – File 24 © Drs. Schwartz & Arroyo EEL 3701 Control Unit Control Unit Program Counter Control Sequence Generator Instruction Register Instruction Decoder Clock ALU Misc. Misc. SDR SAR storage data (buffer) reg storage address reg • Functions > Decodes Instruction > Generates Control Signals > Generates Timing Signals • Hardware > Instruction Register (IR) > Program Counter (PC) > Control Signal Generator >Clock Status Register
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6-Apr-06—4:12 PM 3 3 University of Florida, EEL 3701 – File 24 © Drs. Schwartz & Arroyo GCPU, Comp Org, 68HC11, Assembly EEL 3701 5 University of Florida, EEL 3701 – File 24 © Drs. Schwartz & Arroyo EEL 3701 Arithmetic/Logic Unit (ALU) Arithmetic/Logical Unit (ALU) • Functions > Arithmetic operations on data > Logical operations on data > Shifting operations on data > Status checking on results • Hardware > Arithmetic/Logical circuits > Accumulator >Shifter > Status Register Shifter Accumulator To Memory Status Register Function Code (from Control Unit) Shift/No Shift Left/Right Logical/Arithmetic from C.U. Flags to Control Unit From Memory ALU EEL 3701 6 University of Florida, EEL 3701 – File 24 © Drs. Schwartz & Arroyo EEL 3701 Instruction Register • The n-bit instruction register consists of a MUX and a D-FF. >The MUX has a select line, IR_LD >The output of the MUX goes to the D input of the D-FF >The output of the D-FF is the 0 input of the MUX >The 1 input of the MUX comes from the input bus
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6-Apr-06—4:12 PM 4 4 University of Florida, EEL 3701 – File 24 © Drs. Schwartz & Arroyo GCPU, Comp Org, 68HC11, Assembly EEL 3701 7 University of Florida, EEL 3701 – File 24 © Drs. Schwartz & Arroyo EEL 3701 Programming Model for GCPU 8-bit Accumulators A And B Index (Displacement) Register X Index (Displacement) Register Y Memory Address Register ( Hidden ) MAR Program Counter PC 0 1 Zero Negative N Z Condition Code Register (CCR) IX 0 15 IY 0 15 MAR 0 15 PC 0 15 IR 0 5 A 0 7 B 0 7 Instruction Register ( Hidden ) IR EEL 3701 8 University of Florida, EEL 3701 – File 24 © Drs. Schwartz & Arroyo EEL 3701 Programming Model for Motorola 68HC11 0 7 0 7 A B D0 15 0 15 0 15 0 15 0 15 IX IY SP PC
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This note was uploaded on 02/22/2011 for the course ECON 2023 taught by Professor Rush during the Spring '08 term at University of Florida.

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24 - GCPU_Comp Org_68HC11_Assembly - 6-Apr-064:12 PM GCPU,...

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