Lab 1 Report

Lab 1 Report - Objective(s In this lab the student’s...

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Unformatted text preview: Objective(s): In this lab, the student’s objective is: • “To gain some experience building and debugging combinational circuits using TTL IC’s [1].” • To gain experience using POS and SOP forms. • To gain some experience using exclusive OR operator gates. Expected Outcome(s): The expected outcome is: • To be able to explain the t ruth tables that allows two single bit numbers to be added. • To be familiar with the half adder as to be able to write Boolean algebraic expressions for the sum and carry functions; SOP and POS. • Use TTL hardware to realize SUM and CRY. • Test/Debug TTL using logic probes and LEDs. • Write Boolean algebraic expressions for the full adder. • Build and debug a full adder on a trainer board. A B SUM CRY A' A'B B' AB' Results: Task 1.1 Building the 1-bit Half-Adder Task Statement: The task was to build a 1-bit half adder. Figure 1 – Diagram of IC component A standard IC has 14 pins. The 7 th pin is connected to the ground and the 14 th pin is connected to the high voltage (+5V). For NOT operational gate IC’s, the inputs and outputs alternate so with pin 1 being the input, pin 2 in the output. Pin 3 input = pin 4 output. Pin 13 input = pin 12 output. For the AND, OR and XOR operational gate IC’s, the operation has 2 inputs and 1 output. Therefore, with inputs being pin 1 and pin 2, the output is pin 3. Same with the inputs being pin 13 and pin 12, the output would be pin 11. Figure 1 – Schematic of 1-Bit Half Adder Figure 1 is a schematic of a half adder and our task is to build the above circuit on to a trainer board. Figure 2 – 1-Bit Half Adder Circuit Schematic Wiring on T rainer Board According to the schematic, there are 2 inputs; A and B. They will be considered as SW 1 and SW 2 on the trainer board. From hardware lab 0, we know that the 7 th pin is connected to the ground and the 14 th pin is connected to the high voltage (+5V). For the SUM of a half adder, it requires the NOT of the first input to be AND’d with the second input and the NOT of the second input to be AND’d with the first input. Those two outputs are then OR’d to get the SUM....
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Lab 1 Report - Objective(s In this lab the student’s...

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