Lab 3 Report

Lab 3 Report - Objective(s): In this lab, the students...

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Objective(s): In this lab, the student’s objective is: To gain some experience building o Latches (S-R and D) o Flip-flops (D and J-K) o Registers Learn the operations of the above devices and build a 2-bit binary up-counter [1]. Expected Outcome(s): The expected outcome is: To be able to realize and describe the operation of an S-R and D latch. Describe the difference between an active high and active low latch. Use the J-K and D flip-flop in a circuit Realize a de-bouncing circuit. Realize an arbitrary large resister using J-K flip-flops. Realize a 2-bit binary up-counter using J-K flip-flops. Design a 3-bit binary up-counter using J-K flip-flops [1].
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Results: Task 3.1 Build an Active High S-R Latch Task Statement: The task was to build an incorrect active high S-R latch. In the lab manual, Figure 3-1 shows the schematic of an active-high S-R latch. Input Output Tested Circuit S R + Q + Q + Q + Q 0 0 + Q + Q + Q + Q 0 1 0 1 0 1 1 0 1 0 1 0 1 1 Invalid State 0 0 Table 1 – Function Definition Table of Active-High S-R Latch According to the schematic in the lab manual, 2 NOR gates are used to make an active-high S-R latch. Below is the schematic of the breadboard circuit. Since 2 NOR gates are used, pin 8 though pin 13 will be used as input and output pins. As usual, pin 7 is connected to the ground and pin 14 is connected to +5V. One NOR gate has input R which is connected to pin 8 and the output of the second NOR gate, pin 13, which is connected to pin 9. This produces an output in pin 10 which is connected to LED 1. This output is + Q . This output is the input to the second NOR gate so it is connected to pin 12. The second input is the lone input, input S. These two inputs into a NOR gate gives the output + Q which come from pin 13 and is connected to LED 2. Figure 1 – Schematic of Active High S-R Latch Using a NOR Gate
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When testing the invalid input, the output appears to be 0,0. The logic equation is broken where += + Q notQ . In this task, I learned the function of an active-high S-R latch. In the S-R latch, the input 1,1 is an invalid state while input 0,0 gives the function of stay. Task 3.2 Build a D-Latch Task Statement: The task is to build a D-Latch In the lab manual, Figure 3-2 shows the schematic of a D-latch. Input Output Tested Circuit D + Q + Q + Q + Q 0 0 1 0 1 1 1 0 1 0 Table 2 – Function Definition Table of D-Latch Based on the schematic of the D-latch in the lab manual, the circuit below was built. The S-R latch had two inputs that were either irrelevant (0,0) or invalid (1,1). There are only 2 real inputs (0,1) and (1,0). The inputs are complements of each other so the D-latch has one input where it is used into the inputs of the S-R latch. The left part of the D-latch below is like the S-R latch above in Figure 1. However, the inputs are now based off the D input. The S and R input from SW1 and SW2 are removed from pin 8 and pin 11. SW1 is connected to pin 9 of the 7404, the inverter. It’s output, pin 8 is connected to pin 8 of the
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This note was uploaded on 02/22/2011 for the course EEE 120 taught by Professor Tylavsky during the Fall '10 term at ASU.

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Lab 3 Report - Objective(s): In this lab, the students...

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