Lab 2 Report

Lab 2 Report - Objective(s): In this lab, the students...

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Objective(s): In this lab, the student’s objective is: To build and debug a variety of different circuits Turn those circuits into subcircuits Use the subcircuits to build more circuits that perform special operations Data route using Logic Works Expected Outcome(s): The expected outcome is: To design a 1-bit full adder. o Build it in Logic Works. o Test/Debug it. o Implement it into a subcircuit. To design a 4-bit full adder using the 1-bit full adder subcircuit. o Build it in Logic Works. o Test/Debug it. o Implement it into a subcircuit. To design a 2-1 multiplexer. o Build it in Logic Works. o Test/Debug it. o Implement it into a subcircuit. To design a 4-bit, 2-1 multiplexer. o Build it in Logic Works. o Test/Debug it. o Implement it into a subcircuit. To design a; 1-to-2, 2-to-4, 4-to-16 decoder.
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o Build it in Logic Works. o Test/Debug it. o Implement it into a subcircuit.
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0 1 B 0 1 Cin 0 SUM 0 1 A 1 Results: Task 2.1 Design a Full Adder Using NAND/NAND Logic Task Statement: The task was to design a 1-bit full adder using NAND/NAND logic. Inverters can be used in place of the NAND equivalent. Figure 1 – A Schematic of a 1-Bit Full Adder using NAND gates and NOT gates From the truth table of a 1-bit full adder, we can derive that the SUM Boolean algebraic equation is, = + + + SUM A BCin ABCin ABCin AB Cin . The SUM function requires the inputs A, B and C in to be AND’d in various combinations. The outputs are then OR’d. According to the lab manual, a NAND gate can replace an OR gate and that is what is shown above. The inputs are kept like the ones in the equation because when it passes through the first NAND gate, it is inverted and then it passes through the second NAND gate, it changes back. For example, the top NAND gate, it’s inputs are , A B and Cin . As it passes through the first NAND gate, its result is A BCin . With the equivalent OR gate where the inverters are in the front, it adds another line which cancels out the initial inverting. = A B Cin A B Cin .
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A B Cin SUM CRY As for the CRY function, the truth table gives the Boolean algebra to be = + + CRY AB BCin ACin . Using the same logic as with the SUM function, the value inputs are NAND’s twice to produce the CRY output. In this task, I learned how to build a full adder on Logic Works using NAND/NAND logic. Task 2.2 Build, Debug and Test a 1-bit Full Adder Task Statement: The task was to build a 1-bit Full Adder using NAND/NAND logic for the CRY function and a XOR gate for the SUM function. Debug and test the full adder after its been built. Figure 2 – Schematic of 1-Bit Full Adder with XOR Gate for SUM ad NAND/NAND Logic for CRY The full adder circuit was built with the SUM function being the 3 inputs being XOR’d. The CRY function was built based on the CRY function in Figure 1.
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in A B SUM CRY 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 Table 1 – Truth Table for Testing 1-bit Full Adder The testing truth table matches the truth table in the lab manual. In this task, I learned how to build a 1-bit full adder using an XOR gate and NAND gates.
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This note was uploaded on 02/22/2011 for the course EEE 120 taught by Professor Tylavsky during the Spring '10 term at ASU.

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Lab 2 Report - Objective(s): In this lab, the students...

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