Lab 4 Report

Lab 4 Report - O bjective(s): In this lab, the students...

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Objective(s): In this lab, the student’s objective is: To design three types of memory and the communication bus architecture of a simple microprocessor [1]. Act as the controller to cause it to execute a simple program [1]. Expected Outcome(s): The expected outcome is: To build and debug a simulation of: o A 4-bit register o A 4-bit buffer [1]. To build, debug and control a simulation of: o A central processing unit (CPU) o A ROM o A RAM o An output port o An address decoding circuit [1]. Build and debug a simulation of a microprocessor without a controller. Act as the control that is not present in the build simulation microprocessor. Calculate the maximum clock frequency that may be applied to a synchronous circuit [1].
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Brainless Microprocessor Brainless Microprocessor Function Description and Test Results Schematic 2 – Schematic of Sub-blocks of the Brainless Microprocessor The brainless microprocessor is made up of 5 main components; the CPU which consists of the Arithmetic and Logic Unit (ALU), the accumulator (ACC) and the Buffer, the addressing decoder and the external memory. The CPU has three main parts; the ALU which was built in task 3 does the operations that the control assigns. The second part is the ACC. The ACC is made up of a 4-bit register and the last component was a buffer. The 4-bit register is made up of 4, 1-bit registers. In making the 1-bit register, a JK flip flop was used where the set was high and the reset could be controlled. The J and K inputs were connected to AND gates which had the inputs of data, (D) and D’. An enable input was the second input to the AND gate. This flip flop produced one output. Four 1-bit registers were combined where their clock, enable and data inputs were synchronized. The 4-bit Buffer is a circuit which contains a string 1-bit tri state buffers. There must be two active high enables (E1 and E2) which must both be high to enable the four tri-state outputs. The tri-state buffers are active low, so a NAND gate gives the correct interface. The 4-bit buffer works in a way that; if enabled, send the input through.
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E2 A3 A2 A1 A0 E1 Y3 Y2 Y1 Y0 BUF ER_4 E2 A3 A2 A1 A0 E1 Y3 Y2 Y1 Y0 BUF ER_4 0 1 2 3 8 9 A B C D E F E2 A3 A2 A1 A0 E1 Y3 Y2 Y1 Y0 BUF ER_4 0 1 2 3 4 5 6 7 8 9 A B C D E F E2 A3 A2 A1 A0 E1 Y3 Y2 Y1 Y0 BUF ER_4 0 1 2 3 4 5 6 7 8 9 A B C D E F AD03 AD02 AD01 AD0 A0 A1 A2 A3 A0 A1 A2 A3 A0 A1 A2 A3 A0 A1 A2 A3 4 5 6 7 8 9 A B C D E F DB Read M20 M0 M30 M10 M21 M01 M31 M1 M2 M02 M32 M12 M23 M03 M3 M13 The addressing decoder is the component of the brainless microprocessor that opens the gates to the ports. When data is to be read from a Read Only Memory (ROM) block, the addressing decoder will input a value of 0-3. When a data is to be read from or written to the Random Access Memory (RAM), the addressing decoder will input a value of F and when data is to be written to the output display, the addressing decoder input will be E. For the external memory, there is the RAM, ROM and output display. The ROM is are initial values set by the controller. RAM is the memory that can be stored and read. The
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Lab 4 Report - O bjective(s): In this lab, the students...

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