Lab 5 Report

Lab 5 Report - Objective(s): In this lab, the students...

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Unformatted text preview: Objective(s): In this lab, the students objective is: To complete the design of the microprocessor [1]. To create an instruction set [1]. To enter a program into memory [1]. To execute the program [1]. Expected Outcome(s): The expected outcome is: To design a PROM-based controller for an elementary microprocessor [1]. Create an instruction set for an elementary microprocessor [1]. Use the language of your instruction set to create a program and enter it into your memory [1]. Execute a program on your simulated microprocessor [1]. Operation of Microprocessor There are several differences between the brainless microprocessor and the complete microprocessor. The brainless microprocessor requires someone to control all of its inputs and outputs while the complete microprocessor has an address generation circuit and a controller to manage the work done by the person in the brainless microprocessor. The controller allows the processor to read instructions from memory and control the inputs to the components of the processor. To do this, the instructions are stored in the PROM. The PROM changes the inputs based on the opcode read from the memory. The complete microprocessor contains opcodes for Load the ACC, Add to ACC and Stopping the program. The address generation circuit is the component that accesses the next address in memory. This is so the program in memory can continue to be read and ran. In the first clock pulse, the memory location is read and is ran to the PROM where it then runs an update to the inputs in the areas of the processor which is involved. If the opcode it reads from the memory is an operand, the memory location is incremented and that value is either loaded to the ACC or added to the ACC. These commands continue until the opcode value STOP is read in the memory address. When the STOP value is read, the PROM will enter an infinite loop and can only be reset manually. Figure 1 below shows the schematic of the complete microprocessor. A3 EN A0 A1 A2 Y15 Y14 Y13 Y12 Y11 Y10 Y9 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Y8 DECODER_4 +5V ALU /~A_Only /~Invert Logic/~Arith Cin Cout Y0 Y1 Y2 Y3 B0 B1 B2 B3 A0 A1 A2 A3 A0 A1 A2 A3 B0 B1 B2 B3 A0 A1 A2 A3 CLK EN CLR Y0 Y1 Y2 Y3 REG E2 A3 A2 A1 A0 E1 Y3 Y2 Y1 Y0 BUFFER_4 B0 B1 B2 B3 B0 B1 B2 B3 B0 B1 B2 B3 A0 A1 A2 A3 A0 A1 A2 A3 X X E2 A3 A2 A1 A0 E1 Y3 Y2 Y1 Y0 BUFFER_4 E2 A3 A2 A1 A0 E1 Y3 Y2 Y1 Y0 BUFFER_4 0123 4567 89AB CDEF E2 A3 A2 A1 A0 E1 Y3 Y2 Y1 Y0 BUFFER_4 0123 4567 89AB CDEF E2 A3 A2 A1 A0 E1 Y3 Y2 Y1 Y0 BUFFER_4 0123 4567 89AB CDEF AD03 AD02 AD01 AD00 A0 A1 A2 A3 A0 A1 A2 A3 A0 A1 A2 A3 A0 A1 A2 A3 A0 A1 A2 A3 CLK EN CLR...
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This note was uploaded on 02/22/2011 for the course EEE 120 taught by Professor Tylavsky during the Spring '10 term at ASU.

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Lab 5 Report - Objective(s): In this lab, the students...

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