CMOS-2-Solved

CMOS-2-Solved - CMOS 2 1. 2. Thin masking Oxide Mask 1 (P+...

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CMOS – 2
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1. Thin masking Oxide 2. Mask – 1 (P+ formation) Boron, E=100 KeV, Dose = 1- 5 E15 cm -2 3. n+ Silicon Epitaxy to form buried n+ layer (N+ ~ 1- 5 E19 cm -3 ) 4. n- Silicon Epitaxy to form buried n+ layer (N+ ~ 1- 5 E16 cm -3 ) 5. p- Silicon Epitaxy to form buried n+ layer (N+ ~ 1- 5 E16 cm -3 ) 6. Mask – 2 & use of Anisotropic etching to form the Via holes
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7. Thermal oxidation of Silicon 8 Deposition of thick (1- 2 micrometers) of doped (n+) Polysilicon 9. Use CMP and remove half of the top layer thermal grown oxide to expose the N+ polysilicon in the Vias 10. Use mask – 3 to remove part of the top layer SiO2 using a very controlled anisothropic etchingemove half of the top layer thermal grown oxide to expose the N+ polysilicon in the Vias
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11. Use Mask – 4 to open up window for forming the emitter doping. Use As ion implantation with E = 20 KeV & dose ~ 1- 5 E15 cm -2 12. Deposition of n+ poly Silicon 13. Use Mask – 5 and then a selective etching of Poly Silicon over SiO2.
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14. Mask – 6
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CMOS-2-Solved - CMOS 2 1. 2. Thin masking Oxide Mask 1 (P+...

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