Week-3-Si-Wafers-I

Week-3-Si-Wafers-I - EE-504L :Solid State Processing and...

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EE-504L :Solid State Processing and Integrated Circuit Laboratory Dr. Kian Kaviani sieh Ming Dept of Electrical Engineering Hsieh Ming Dept. of Electrical Engineering University of Southern California iterbi School of Engineering Viterbi School of Engineering 1/3/2011 Dr. Kian Kaviani, Spring 2011 - EE504L 1
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Silicon Wafer Preparation 1/3/2011 Dr. Kian Kaviani, Spring 2011 - EE504L 2
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rom Sand to EGS From Sand to EGS 1/3/2011 Dr. Kian Kaviani, Spring 2011 - EE504L 3
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hoklarski Pulling from the Melt Choklarski Pulling from the Melt 1/3/2011 Dr. Kian Kaviani, Spring 2011 - EE504L 4
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hoklarski Technique Choklarski Technique 1/3/2011 Dr. Kian Kaviani, Spring 2011 - EE504L 5
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Choklarski Technique 1/3/2011 Dr. Kian Kaviani, Spring 2011 - EE504L 6
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hoklarski Technique: Doping Choklarski Technique: Doping he segregation coefficients of different The segregation coefficients of different dopants decide the ease of doping of the got ingot. Impurity Al As B C Cu Fe O P Sb K 0 0.002 0.3 0.8 0.007 0.0004 0.000008 1.25 0.35 0.023 1/3/2011 Dr. Kian Kaviani, Spring 2011 - EE504L 7
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afer Flats and Notch Wafer Flats and Notch 1/3/2011 Dr. Kian Kaviani, Spring 2011 - EE504L 8
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Slicing the Ingot into Wafers 1/3/2011 Dr. Kian Kaviani, Spring 2011 - EE504L 9
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rinding the Edges of the Wafer Grinding the Edges of the Wafer 1/3/2011 Dr. Kian Kaviani, Spring 2011 - EE504L 10
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rinding the Edges of the Wafer Grinding the Edges of the Wafer 1/3/2011 Dr. Kian Kaviani, Spring 2011 - EE504L 11
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afer Laser Marking Wafer Laser Marking 1/3/2011 Dr. Kian Kaviani, Spring 2011 - EE504L 12
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Requirement for the Silicon Wafers in for the ULSI Era Property Choklarski Requirement for ULSI Resistivity (N – type) 1 – 50 5 – 50 & Up Resistivity (P – type) 0.005 – 50 5 – 50 & Up Resistivity Gradient (%) 5% – 10 % < 1% y( ) Oxygen (ppma) 5 – 25 Uniform & Controlled arbon (ppma) 01 Carbon (ppma) 1 – 5 < 0.1 Dislocation (per cm2) < 500 < 1 Diameter (mm) Up to 300 Up to 300 Wafer Bow ( µ m) < 25 < 5 Surface Flatness ( µ m) < 5< 1 1/3/2011 Dr. Kian Kaviani, Spring 2011 - EE504L 13 Heavy Metal Impurities < 1 ppb < 0.001 ppb
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efects in Crystalline Materials Defects in Crystalline Materials here are four types of crystalline defects There are four types of crystalline defects in Silicon: – 1: Point Defects, 0 dimension - 2: Line Defects, 1 dimensional – 3: Area Defects, 2 dimensional – 4: Volume Defects, 3 dimensional 1/3/2011 Dr. Kian Kaviani, Spring 2011 - EE504L 14
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efects in Crystalline Materials Defects in Crystalline Materials Point Defects : (a) Schottky defects ) terstitial arriving from the surface (b) Interstitial arriving from the surface (c) Frenkel defects 1/3/2011 Dr. Kian Kaviani, Spring 2011 - EE504L 15
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oint Defects: chottky Defects Point Defects: Schottky Defects quilibrium Concentration of Schottky defects Equilibrium Concentration of Schottky defects (N v ): N v =N 0 exp(-Ea/KT), where N 0 = 5E22 p( ), t T = 300 K, N =5E- 2 /cm At T 300 K, N v 5E 12 /cm 3 At T = 1000 K, N v = 5E10 /cm 3 (22 order of magnitude increase !!) 1/3/2011 Dr. Kian Kaviani, Spring 2011 - EE504L 16
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oint Defects: elf terstitial Point Defects: Self Interstitial rankel defects (b) involve creation of two Frankel defects (b) involve creation of two defects (a vacancy and and an interstitial) • Schottky defects involve formation one defect (formation of one vacancy in the lattice) 1/3/2011 Dr. Kian Kaviani, Spring 2011 - EE504L 17
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Week-3-Si-Wafers-I - EE-504L :Solid State Processing and...

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