Week-5-Lith1-1

Week-5-Lith1-1 - EE-504L:Solid State Processing and...

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EE-504L :Solid State Processing and I t t d Ci it L b t Integrated Circuit Laboratory Dr. Kian Kaviani Hsieh Ming Dept of Electrical Hsieh Ming Dept. of Electrical Engineering University of Southern California Viterbi School of Engineering 1/3/2011 Dr. Kian Kaviani Spring 2011 - EE504L 1
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Lithography: SIA Road map Year of the first DRAM Shipment 1999 2003 2006 2009 2012 DRAM Bits/Chip 1 G 4 G 16 G 64 G 256 G Minimum Feature (nm) 140 100 70 50 35 Defect Density (per layer /m # ) 80 60 50 40 30 Defect Size (nm) 60 40 30 20 15 DRAM Chip Size (mm # ) 400 560 790 1120 1580 MPU Chip Size (mm # ) 360 430 520 620 750 Field Size (mm) 25X32 25X36 25X40 25X44 25X52 Exposure Technology 248 nm 248 nm 193 nm 193 nm ? DUV DUV DUV DUV ? Minimum Mask Count 22/24 24 24/26 26/28 28 1/3/2011 Dr. Kian Kaviani Spring 2011 - EE504L 2
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Photolithography – I Photolithography I Photoresist Processing and Material Issues 1/3/2011 Dr. Kian Kaviani Spring 2011 - EE504L 3
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