Week-15-DC-Testing-1

Week-15-DC-Testing-1 - Electrical Characterization of the Finished Wafers th Fi Part II II Dr Kian Kaviani Kian Kaviani Hsieh Ming Electrical

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Electrical Characterization of the Finished Wafers art Part II r Kian Kaviani Dr. Kian Kaviani Hsieh Ming Electrical ngineering USC Viterbi School Engineering USC Viterbi School of Engineering 1/3/2011 Dr. Kian Kaviani - Spring 2011 EE504L 1
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Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) 1/3/2011 Dr. Kian Kaviani - Spring 2011 EE504L 2
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Assumptions used for MOSFET Model 1. We assume that we have long channels (L > 5 micrometer) 2. We assume the mobility of electrons is constant in the channel. e assume that the shape of the channel (same as the MOS inversion 3. We assume that the shape of the channel (same as the MOS inversion layer) as a function of the drain – source bias changes linearly ( g radual c hannel a pproximation , GCA ). urthermore we assume the electric along the channel is the dominant 4. Furthermore, we assume the electric along the channel is the dominant electric field and the component of electric perpendicular to the channel inside the semiconductor is negligible. For long channel MOSFETs this is a fairly good approximation. 1/3/2011 Dr. Kian Kaviani - Spring 2011 EE504L 3
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Characteristics of MOSFETs I V Characteristics of MOSFETs 1/3/2011 Dr. Kian Kaviani - Spring 2011 EE504L 4
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quare Law Model: inear Regime Square Law Model: Linear Regime where: Ids : Drain – to - source current [A] µ : Average mobility of carriers in the channel [cm 2 /V.sec] C 0 : Capacitance per unit area of the MOS structure [F/cm 2 ] W : MOSFET Width ( µ m) L : MOSFET Gate Length ( µ m) V gs : Gate –to-Source Voltage [V] V th : Threshold Voltage [V] Drain ource Voltage [V] 1/3/2011 Dr. Kian Kaviani - Spring 2011 EE504L 5 V ds : Drain-to-Source Voltage [V]
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inear aturation Transition Linear Saturation Transition he above relationship represent the “linear The above relationship represent the linear region” of the MOSFET I – V characteristic, shown in the figure. • In the regime of Vds > (V ds ) sat , where (V ds ) sat = V dss represent the drain – to-source voltage, beyond which any increase in the value of V ds would not bring about any further increase in the I ds . This regime is called saturation regime.
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This note was uploaded on 02/23/2011 for the course EE 474 taught by Professor Lingo during the Spring '11 term at USC.

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Week-15-DC-Testing-1 - Electrical Characterization of the Finished Wafers th Fi Part II II Dr Kian Kaviani Kian Kaviani Hsieh Ming Electrical

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