cs503-lecture3

cs503-lecture3 - Shared Memory Parallel Programming with...

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Shared Memory Parallel Programming with Threads --Pthreads and OpenMP -- Jacqueline Chame and Robert Lucas CSCI503 Spring 2011
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Updated schedule Jan 10 Introduction to parallel programming Assignment: hw1, due: Jan 24 Jan 17 University holiday Jan 24 Single node performance Jan 31 Threads: OpenMP, Pthreads Assignment: hw2, due ? Feb 7 MPI Assignment hw3, due ? Feb 14 MPI, Algorithms Assignment: hw4, due Feb 28 Feb 21 University holiday Feb 28 MapReduce Assignment: hw4, due: March 11 Mar 7 Data parallel (SIMD, CUDA) Assignment: Project Proposal Mar 14 Spring Break Mar 21 Algorithms Due: Project Proposal Mar 28 Partitioned Global Address Space (PGAS) Feedback: Project Proposal Apr 4 Tuning performance of parallel programs Assignment: Final Project Apr 11 Parallel I/O Apr 18 Heterogeneous systems Apr 25 Final Project Presentations
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Outline Shared-memory programming model Threads programming model Threads implementations Pthreads slides based on lecture by Kathy Yelick, UC Berkeley/LBNL OpenMP Slides based on lectures by Ruud van der Pas, Sun Microsystems, and Tim Mattson, Intel.
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Shared memory architectures All processors can access all memory as a global address space. Multiple processors can operate independently but share the same memory resources. Changes in a memory location effected by one processor are visible to all other processors. Shared memory machines can be divided into two main classes based upon memory access times: UMA and NUMA .
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Uniform Memory Access (UMA): Most commonly represented today by Symmetric Multiprocessor (SMP) machines Identical processors Equal access and access times to memory Sometimes called CC-UMA - Cache Coherent UMA. Cache coherent means if one processor updates a location in shared memory, all the other processors know about the update. Cache coherence is accomplished at the hardware level. CPU CPU CPU CPU MEMORY
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Shared Memory (NUMA) Often made by physically linking two or more SMPs One SMP can directly access memory of another SMP Not all processors have equal access time to all memories Memory access across link is slower If cache coherence is maintained, then may also be called CC- NUMA - Cache Coherent NUMA CPU CPU CPU CPU MEMORY CPU CPU CPU CPU MEMORY CPU CPU CPU CPU MEMORY CPU CPU CPU CPU MEMORY
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Program is a collection of threads of control. Can be created dynamically, mid-execution, in some languages Each thread has a set of private variables, e.g., local stack variables Also a set of shared variables, e.g., static variables, shared common blocks, or global heap. Threads communicate implicitly by writing and reading shared variables. Threads coordinate by synchronizing on shared
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This note was uploaded on 02/24/2011 for the course CSCI 503 taught by Professor Hall during the Spring '08 term at USC.

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cs503-lecture3 - Shared Memory Parallel Programming with...

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