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Verilog_Chapter1_Introduction

Verilog_Chapter1_Introduction - NATIONAL UNIVERSITY OF HO...

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NATIONAL UNIVERSITY OF HO CHI MINH CITY UNIVERSITY OF INFORMATION TECHNOLOGY FACULTY OF COMPUTER ENGINEERING LECTURE VERILOG Subject: 1 Lecturer: Lam Duc Khai Hardware Description Language Chapter1: Introduction
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Agenda 1. Chapter 1: Introduction ( Week1) 2. Chapter 2: Fundamental concepts (Week1) 3. Chapter 3: Modules and hierarchical structure (Week2) 4. Chapter 4: Primitive Gates – Switches – User defined primitives (Week2) 2 5. Chapter 5: Structural model (Week3, Week4) 6. Chapter 6: Behavioral model – Combination circuit and Sequential circuit (Week4, 5) 7. Chapter 7: Tasks and Functions (Week6) 8. Chapter 8: State machines (Week6) 9. Chaper 9: Testbench and verification (Week7) 10. Project presentation ( Week7, Week8)
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Contents Chapter 1: Introduction head2right Requirements – Projects – Scores head2right Verilog – What and Why ? head2right CAD flow 3
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Requirement head2right Must be punctual on both class and laboratory. An excess of 15 minutes is not accepted for any reason. head2right Class : Start at 1:00 PM on Tuesday. head2right Laboratory : Start at 8:00 AM and 1:00 PM as schedual. 4 head2right Project : head2right Submit strictly as the deadline through email: [email protected] head2right Name of project file and email subject must abide by the following format, any others format are not accepted: “Project name_maingroup_subgroup_date”
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Projects Projects : Group1: A Floating Point Unit for Numerical Calculations. Group2: Real-time Light-Saber Generator Group3: Real-time Video Processing Group4: FPGA Video Game 5 Group5: Real-time Face Detection Group6: Gestural Interface for Image Browsing Group7: Gesture Recognition Remote Control Group8: Hardware Platform for JPEG Compression/Decompression Reference : http://web.mit.edu/6.111/www/
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Scores Grading system: – Final exam : 4 scores – Projects : 3 scores (documentation + presentation) – Laboratory : 3 scores ( preparation + report + 6 exam) Note: These above scores will only be valid if student attends the laboratory class fully.
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Verilog learning “tips” Verilog is essentially a programming language – similar to C with some Pascal-like constructs The best way to learn any programming language is from live code We will get you started by going through several example programs and explaining the key concepts We will not try to teach you the syntax line-by-line : pick up what you 7 need from the books and on-line tutorials Tip : Start by copying existing programs and modifying them incrementally making sure you understand the output behavior at each step Tip : The best way to understand and remember a construct or keyword is to experiment with it in code , not by reading about it We shall not design at the switch (transistor) level in this course – the lowest level we shall reach is the gate level. The transistor level is more appropriate for an electronics-oriented course
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History HDL History 1970s: First HDLs Late 1970s: VHDL VHDL = VHSIC HDL = Very High Speed Integrated Circuit HDL
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  • Spring '11
  • a
  • Electronic design automation, CAD flow, Pre-synthesis verification Compilation, Description Pre-synthesis verification

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