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CAD assignment # 1

CAD assignment # 1 - CS/EE 5830/6830 CAD Assignment#1 Due...

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CS/EE 5830/6830 -- CAD Assignment #1 Due Tuesday, January 25th, 5:00pm Put assignments in the slot outside the SoC office For this assignment you’ll use Digital VLSI Chip Design with Cadence and Synopsys CAD Tools. The book is available at many on-line booksellers including Amazon. The required chapters from this book are also on the class web site. You’ll need to look at Chapters 1-4 for this assignment. The chapters are tutorial in nature so you should be able to follow along as you’re trying out the tools. I recommend that you don’t print them out. They’re somewhat long because of the step-by-step nature of the tutorials. Instead I’d open the chapters in your browser in one window, start Cadence in another window, and follow along on the screen. If you have a print copy of the book, that works too. Note that the book, and the online chapters, are for a slightly different version of the Cadence tools. The book uses the v5.1.41 tools, and we are now using the v6.1.4 tools. Most things look and work very much the same, but you might find dialog boxes that are slightly different than in the book. It should be relaitvely easy to figure out what the difference is. I should have a v6.1.4 update sometime soon also. First read Chapters 1 and 2 to get a picture of how the Cadence CAD tools are organized, and how you should set things up for using the tools. Then do the following: 1. Complete the first part of the Cadence Composer tutorial in Chapter 3 by making a new library and designing a Full Adder using the standard cells in the UofU_Digital_v1_2 library. Note that this is a slightly different parts library than used in the CAD book tutorial! Pay attention to where your gates are coming from! You are welcome to use the same schematic as is used in the CAD
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