Cad tools book ( contents )

Cad tools book ( contents ) - Digital VLSI Chip Design with...

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Unformatted text preview: Digital VLSI Chip Design with Cadence and Synopsys CAD Tools Erik Brunvand School of Computing University of Utah ii DRAFT (January 11, 2009) Please do not distribute iii To Sandy and Scruggs DRAFT (January 11, 2009) Please do not distribute iv DRAFT (January 11, 2009) Please do not distribute Contents 1 Introduction 1 1.1 CAD Tool Flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.1.1 Custom VLSI and Cell Design Flow . . . . . . . . . . . . . . . . 3 1.1.2 Hierarchical Cell/Block ASIC Flow . . . . . . . . . . . . . . . . 3 1.2 What This Book Is and Isnt . . . . . . . . . . . . . . . . . . . . . . . . 4 1.2.1 Bugs in the Tools? . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.3 Tool Setup and Execution Scripts . . . . . . . . . . . . . . . . . . . . . . 5 1.4 Typographical Conventions . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 Cadence DFII and ICFB 9 2.1 Cadence Design Framework . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2 Starting Cadence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.3 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3 Composer Schematic Capture 17 3.1 Starting Cadence and Making a New Working Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.2 Creating a New Cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.2.1 Creating the Schematic View of a Full Adder . . . . . . . . . . . 19 3.2.2 Creating the Symbol View of a Full Adder . . . . . . . . . . . . . 26 3.2.3 Creating a Two-bit Adder Using the FullAdder Bit . . . . . . . . 28 3.3 Schematics that Use Transistors . . . . . . . . . . . . . . . . . . . . . . 31 3.4 Printing Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.4.1 Modifying PostScript Plot Files . . . . . . . . . . . . . . . . . . 38 vi CONTENTS 3.5 Variable, Pin, and Cell Naming Restrictions . . . . . . . . . . . . . . . . 39 3.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 4 Verilog Simulation 41 4.1 Verilog Simulation of Composer Schematics . . . . . . . . . . . . . . . . 44 4.1.1 Verilog-XL : Simulating a Schematic . . . . . . . . . . . . . . . . 45 4.1.2 NC Verilog : Simulating a Schematic . . . . . . . . . . . . . . . . 64 4.2 Behavioral Verilog Code in Composer . . . . . . . . . . . . . . . . . . . 72 4.2.1 Generating a Behavioral View . . . . . . . . . . . . . . . . . . . 73 4.2.2 Simulating a Behavioral View . . . . . . . . . . . . . . . . . . . 76 4.3 Stand-Alone Verilog Simulation . . . . . . . . . . . . . . . . . . . . . . 76 4.3.1 Verilog-XL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 4.3.2 NC Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 4.3.3 VCS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 4.4 Timing in Verilog Simulations . . . . . . . . . . . . . . . . . . . . . . . 90 4.4.1 Behavioral Versus Transistor Switch Simulation . . . . . . . . . . 94 4.4.24....
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Cad tools book ( contents ) - Digital VLSI Chip Design with...

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