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Unformatted text preview: Chapter 3 Composer Schematic Capture C OMPOSER is the schematic capture tool that is bundled with the the Cadence Design Framework II ( DFII ) tool set. It is a full-featued schematic capture tool that well Although the schematic tool is called Composer in the documentation, its called Virtuoso Schematic Editing in the window title. Its part of the Virtuoso tool suite. use for designing transistor-level schematics for small cells, gate-level schematics for larger circuits, and schematics containing a mix of gates and Verilog code for more complex circuits. In that case, some of the components in the schematic will contain tran- sistors at the lowest level, and some will contain Verilog code. Because the simulators that are used in conjunction with Composer are all Verilog simulators, these mixed schematics can be simulated using the same simulators used by schematics with only gates or transis- tors. I find schematics extremely useful for all levels of design. Even for designs that are done completely in Verilog code, I find that connecting the Verilog components in a schematic often makes things easier to understand than large pieces of code where con- nections are made with large argument lists and named wires. Your mileage may vary, of course. Composer has connections to all sorts of other tools in the DFII tool suite, and to other Composer is a part of the IC v5.1.41 tools. tool suites. Well look at all of them in later chapters. Composer is integrated with the Verilog-XL and NC Verilog simulators so that you A file that captures the component and connection information for a circuit is called a netlist, and the process of generating that file is called netlisting. can automatically export a schematic to a simulator. The Composer /Verilog integra- tion will take your schematic and generate a Verilog netlist for simulation, and also build a simple testbench wrapper as a Verilog file that you can modify with your own testing commands. Well see how that works in Chapter 4. Composer has a connection with the Cadence Virtuoso-XL layout tool so that the designer can see the connection between the layout and the schematic. This can be used as a guide for producing a layout based on a schematic using Virtuoso-XL , and 18 CHAPTER 3: Composer Schematic Capture is also a mechanism for specifying the connectivity of a circuit when using the ICC Chip Assembly Router to assemble large chip pieces. Well see this in Chapter 12. Theres also a connection to the Affirma Analog Environment , which is an interface to the Cadence Spectre analog simulation tool (Chapter 7). Using this interface you can, for example, pick circuit nodes from your schematic to be plotted in the analog simulation output file. This connection will also generate the required Spectre or Spice netlist from your schematic automatically....
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- Fall '11