Chapter4

Chapter4 - Chapter 4 Verilog Simulation A HARDWARE...

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Unformatted text preview: Chapter 4 Verilog Simulation A HARDWARE DESCRIPTION LANGUAGE (HDL) is a programming language de- signed specifically to describe digital hardware. Typical HDLs look somewhat like software programming languages in terms of syntax, but have very different semantics for interpreting the language statements. Digital hardware, when examined at a sufficient level of detail, can be described as a set of Boolean operators executing concur- rently. These Boolean operators may be complex Boolean functions, refined into sets of Boolean gates (NAND, NOR, etc.), or described in terms of the individual transistors that implement the functions, but fundamentally digital systems operate through the combined effect of these Boolean operators executing at the same time. There may be a few hundred gates or transistors, or there may be tens of millions, but because of the concurrency in- herent in these systems, an HDL used to describe these systems must be able to support this sort of concurrent behavior. Of course, they also support “software-like” sequential behavior for high-level modeling, but they must support the very concurrent behavior of the fine-grained descriptions. To enable this sort of behavior, HDLs are typically executed through event-driven sim- ulators. An event-driven simulator uses a notion of simulation time and an event-queue to schedule events in the system being described. Each HDL construct has inputs and out- pust (think of a construct as modeling a single gate, for example, but it could be much more complex than that). The description of the construct includes not only the function of the construct, but also how the construct reacts over time. If a signal changes then the event-queue looks up which constructs are affected by that change to know which code to run. That code may produce a new event at the construct’s output, and that output event will be sent to the event queue so that the output event will happen sometime in the future. When simulation time advances to the correct value, the output event occurs, which may cause other activity in the described system. The event-queue is the central controlling structure that enables the HDL program to behave like the hardware that it is describing. So, although you may think of “running a program” written in a software programming 42 CHAPTER 4: Verilog Simulation language, it’s more correct to think of “running a simulation” when executing an HDL program. Verilog is one of the two most widely used HDLs with VHDL being the other main HDL in wide use today. Much of the simulation information described in this chapter will One reason to choose Verilog is that some of the tools in this CAD flow (place and route in particular) require Verilog as an input specification....
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This note was uploaded on 02/24/2011 for the course ECE 6710 taught by Professor Dr.erikbrunvand during the Fall '11 term at Utah.

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Chapter4 - Chapter 4 Verilog Simulation A HARDWARE...

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