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Unformatted text preview: Chapter 5 Virtuoso Layout Editor V IRTUOSO is the editor from Cadence that is used to draw the composite layout for the fabrication of your circuit. It is part of the DFII tool suite. The process of Virtuoso is a part of the IC v5.1.41 tools. drawing layout amounts to drawing lots of colored rectangles with a graphical editor where each color corresponds to a fabrication layer on the integrated circuit. There are a lot of design rules for how those layers interact, and they must be followed very care- fully. The circuit described by these colored rectangles can be extracted from this graphic version and compared to the transistors in the schematic. The layout is eventually exported in standard format called Stream or GDSII and sent to the foundry to be fabricated. Note that this chapter will not attempt to explain the electrical function of each of the CMOS layout layers. Nor will it explain how to use these layers to design electrical com- ponents. It is limited to a description of how the Virtuoso tool is used to draw those layers. The question of how to use those layers to design a particular electrical component can be found in VLSI design textbooks. I assume, for example, that you know that transistors are designed by overlapping active layers (n-type or p-type material) with polysilicon, and that those transistors must also be placed inside a lightly doped region of the correct type (p-substrate or nwell). You should also know about the metal layers used for interconnec- tions, and how contacts and vias are used to make connections between the metal layers and from the metal layers to polysilicon and active layers. These, and many more details of how the CMOS layers interact when fabricated, are covered in detail in many VLSI design textbooks. See Weste and Harris  and Rabaey  as just two examples. This chapter will show how to to use the Virtuoso Layout Editor to draw the composite layout and how to check that the layout obeys design rules using Design Rule Checking ( DRC ). Its also critical that the layout correspond to the schematic that you wanted. A Layout Versus Schematic ( LVS ) process will check that the extracted circuit from your layout matches the transistor schematic that you wanted. What were after is for all the dif- ferent views of a cell to match in terms of their information about the cell. The schematic or cmos sch view should describe the same circuit that the layout view describes, the sym- 110 CHAPTER 5: Virtuoso Layout Editor bol view should have the same interface as both of those views, and the behavioral view should also share that interface. Eventually well add extracted and abstract views from other tools, which should also match the essential information. You may also use config views for analog simulation....
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This note was uploaded on 02/24/2011 for the course ECE 6710 taught by Professor Dr.erikbrunvand during the Fall '11 term at University of Utah.
- Fall '11