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Unformatted text preview: Chapter 6 Standard Cell Design Template D ESIGNING a standard cell library involves creating a set of cells (gates, flip flops, etc.) that work together throughout the CAD tool flow. In general this means that the cells should have all the views necessary for designing with the cells, and should be compatible in terms of their attributes so that they can all work together. At this point in our understanding of the CAD flow, this means that each cell in the cell library needs the following views: schematic or cmos sch: This view describes the gate- or transistor-level definition of the cell. It can be simulated using any of the Verilog simulators in Chapter 4 as a switch- level or a behavioral-level simulation. behavioral: This view is the Verilog description of the cell. It should include both be- havior and specify blocks for timing so that the timing can be back-annotated with better estimates as the design progresses through the flow. layout: This view describes the mask layout of the cell. It should pass all DRC checks. It also should follow strict physical and geometrical standards so that the cells will fit with each other and work together (the subject of this chapter). extracted: This view extracts the circuit netlist from the layout and is generated by the extraction process. It should be used with the LVS checker to verify that the layout and schematic or cmos sch views represent the same circuit. analog-extracted: This view is an augmented version of the extracted view that includes information allowing it to be used by the analog simulator Spectre . It is generated from the extracted view through the LVS process. In addition to these views, subsequent chapters in this text will introduce a number of other views that are required for the final, complete cell library. They include: 156 CHAPTER 6: Standard Cell Design Template abstract: This view is derived from the layout. It tells the place and route tool where the ports of the cell are, and where the “keepouts” or obstructions of the cell are that it should not try to route over. Generating this view from the layout is described in Chapter 10. LEF: This Library Exchange Format file is derived from the abstract view of the cell. It is read by the place and route tool ( SOC Encounter ) so that it can get information about the technology that it is routing in, and also about the abstract views of the cells in the library. This view is generated by the Abstract program. Verilog interface: The system you design will eventually be input to the place and route tool as a structural Verilog file that describes the standard cell gates used in your design and the connections between them. In addition to this file, you need a simple I/O interface of each cell (separate from the LEF file) so that the place and route tool can parse the structural Verilog file. This will also be described in Chapter 10....
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- Fall '11
- Gate, Electronic design automation, Vdd, Cadence, Standard cell