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Unformatted text preview: Chapter 9 Verilog Synthesis S YNTHESIS is the process of taking a behavioral Verilog file and converting it to a structural file using cells from a standard cell library. In other words, the behavior that is captured by the Verilog program is synthesized into a circuit that behaves in the same way. The synthesized circuit is described as a collection of cells from the target cell library . This Verilog file is known as structural because it is strictly structural instantiations of cells from the library. It is the Verilog text equivalent of a schematic. This structural file can be used as the starting point for the back-end tools that will place those cells on the chip and route the wire connections between them. There are many different Verilog synthesis tools available in the CAD market. Any of them that use Liberty files to describe cell behavior would be usable in our flow. In partic- ular, the Cadence synthesis system is called RTL Compiler and the synthesis system from Synopsys is called Design Compiler . Both are very capable synthesis systems, but because many engineers use Synopsys Design Compiler , even when they are using Cadence tools for other things, Ill describe that one first. 9.1 Synopsys Design Compiler Synthesis with dc shell This is the flagship synthesis tool from Synopsys. It comes in two flavors: dc shell , which Tcl stands for Tool Command Language and is a standard syntax for providing input commands to tools. has a Tcl shell-command interface, and Design vision , which is a GUI window/menu- driven version. The dc shell version is often driven by writing scripts and executing those scripts on new designs. Well also use the arithmetic circuit descriptions in the Synopsys DesignWare library. In a switch from other chapters, where we start with the GUI before using scripts, we will demonstrate the synthesis portion of the flow by starting with the text-based dc shell version of Design Compiler . First, an extremely basic script will be used just to demon- 258 CHAPTER 9: Verilog Synthesis strate basic principles. This script will then be expanded to include more features of the synthesis procedure. Only then will we introduce the GUI version. This is because script- These examples use Design Compiler from the y-2006.06 and z-2007.03 releases. ing is by far the most common way designers use these synthesis tools. 9.1.1 Basic Synthesis In order to make use of Synopsys synthesis, you need (at least) the following files: .synopsys dc.setup: This is the setup file for Design Compiler . A simple version of this file is shown in Figure 9.1. Note that it has a dot as the first character in the file name. You should copy this file into the directory from which you plan to run the Synopsys tools....
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This note was uploaded on 02/24/2011 for the course ECE 6710 taught by Professor Dr.erikbrunvand during the Fall '11 term at University of Utah.
- Fall '11