DerekChiou_EE306_Spring2009_Lecture6

DerekChiou_EE306_Spring2009_Lecture6 - Derek Chiou 306:...

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Unformatted text preview: Derek Chiou 306: Logical Equations, M emor y, and State M achines Prof. Derek Chiou University of Texas at Austin Adminstr ation Syllabus reminder http://spreadsheets.google.com/ccc?key=p_AK28TVsrOsmx-l2d2XfL 2/9/2009 Derek Chiou : EE306: Lecture 6 2/9/2009 Derek Chiou : EE306: Lecture 6 Recap & Outline Recap Floating point with an exponent of all 1s Truth tables to logical equations Continuing with gates Outline Truth tables to logical equations PLA R-S Latch, Gate D latch, Register Memory Tr uth Tables to Logical Equations Full adder 2/9/2009 Derek Chiou : EE306: Lecture 6 PLA Str uctur e 2/9/2009 Derek Chiou : EE306: Lecture 6 Stor age: RS Latch 2/9/2009 Derek Chiou : EE306: Lecture 6 Stor age: RS Latch 2/9/2009 Derek Chiou : EE306: Lecture 6 Gated D Latch 2/9/2009 Derek Chiou : EE306: Lecture 6 Register 2/9/2009 Derek Chiou : EE306: Lecture 6 M emor y Address space Number of locations Addressibility Number of bits per location 2/9/2009 Derek Chiou : EE306: Lecture 6 A Simple M emor y 2/9/2009 Derek Chiou : EE306: Lecture 6 Reading M emor y 2/9/2009 Derek Chiou : EE306: Lecture 6 State...
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DerekChiou_EE306_Spring2009_Lecture6 - Derek Chiou 306:...

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