DerekChiou_EE306_Spring2009_Lecture6

DerekChiou_EE306_Spring2009_Lecture6 - Register Memory l...

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© Derek Click to edit Master subtitle style 2/9/2009 © Derek Chiou : EE306: Lecture 6 306: Logical Equations and Gates Prof. Derek Chiou University of Texas at Austin
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Adminstration l Syllabus reminder l http://spreadsheets.google.com/ccc?key=p_AK28TVsrOsmx-l2
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l Recap l Floating point with an exponent of all 1s l Truth tables to logical equations l Continuing with gates l Outline l Truth tables to logical equations l PLA l R-S Latch, Gate D latch, Register l Memory
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Truth Tables to Logical Equations l Full adder
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PLA Structure
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Storage: RS Latch
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Storage: RS Latch
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Gated D Latch
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Unformatted text preview: Register Memory l Address space l Number of locations l Addressibility l Number of bits per location A Simple Memory Reading Memory Sequential Logic Circuit Finite State Machines l 1. a finite number of states l 2. a finite number of external inputs l 3. a finite number of external outputs l 4. an explicit specification of all state transitions l 5. an explicit specification of what determines each external output value State l A snapshot in time of all relevant elements of a system l All memory locations...
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This note was uploaded on 02/24/2011 for the course EE 306 taught by Professor Ambler during the Spring '07 term at University of Texas at Austin.

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DerekChiou_EE306_Spring2009_Lecture6 - Register Memory l...

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