cs2100-8-Sequential-Logic

cs2100-8-Sequential-Logic - CS2100Computer Organisation...

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CS2100 Computer  Organisation http://www.comp.nus.edu.sg/~cs2100/ Sequential Logic (AY2009/2010) Semester 2
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CS2100 Sequential Logic 2 WHERE ARE WE NOW? Number systems and codes Boolean algebra Logic gates and circuits Simplification Combinational circuits Sequential circuits Performance Assembly language The processor: Datapath and control Pipelining Memory hierarchy: Cache Input/output Preparation: 2 weeks Logic Design: 3 weeks Computer organisation
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CS2100 Sequential Logic 3 SEQUENTIAL LOGIC Memory Elements Latches: S-R Latch, D Latch Flip-flops: S-R flip-flop, D flip-flop, J-K flip-flops, T flip-flops Asynchronous Inputs Synchronous Sequential Circuit: Analysis and Design Memory Memory Unit Read/Write Operations Memory Arrays
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CS2100 Sequential Logic 4 INTRODUCTION (1/2) Two classes of logic circuits Combinational Sequential Combinational Circuit Each output depends entirely on the immediate (present) inputs. Combinational Logic : : inputs outputs : : Sequential Circuit Each output depends on both present inputs and state. Memory Combinational Logic : : inputs outputs : :
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CS2100 Sequential Logic 5 INTRODUCTION (2/2) Two types of sequential circuits: Synchronous : outputs change only at specific time Asynchronous : outputs change at any time Multivibrator: a class of sequential circuits Bistable (2 stable states) Monostable or one-shot (1 stable state) Astable (no stable state) Bistable logic devices Latches and flip-flops . They differ in the methods used for changing their state.
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CS2100 Sequential Logic 6 MEMORY ELEMENTS (1/3) Memory element : a device which can remember value indefinitely, or change value on command from its inputs. command Memory element stored value Q Characteristic table : Command (at time t ) Q(t) Q(t+1) Set X 1 Reset X 0 0 0 Memorise / No Change 1 1 Q(t) or Q : current state Q(t+1) or Q + : next state
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CS2100 Sequential Logic 7 MEMORY ELEMENTS (2/3) Memory element with clock. Clock is usually a square wave. command Memory element stored value Q clock Positive edges Negative edges Positive pulses
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CS2100 Sequential Logic 8 MEMORY ELEMENTS (3/3) Two types of triggering/activation Pulse-triggered Edge-triggered Pulse-triggered Latches ON = 1, OFF = 0 Edge-triggered Flip-flops Positive edge-triggered (ON = from 0 to 1; OFF = other time) Negative edge-triggered (ON = from 1 to 0; OFF = other time) Positive edges Negative edges Positive pulses
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CS2100 Sequential Logic 9 S-R  LATCH (1/3) Two inputs: S and R . Two complementary outputs : Q and Q' . When Q = HIGH, we say latch is in SET state. When Q = LOW, we say latch is in RESET state. For active-high input S-R latch (also known as NOR gate latch) R = HIGH and S = LOW Q becomes LOW (RESET state) S = HIGH and R = LOW Q becomes HIGH (SET state) Both R and S are LOW No change in output Q Both R and S are HIGH Outputs Q and Q' are both LOW (invalid!) Drawback: invalid condition exists and must be avoided.
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This note was uploaded on 02/27/2011 for the course CS 2100 taught by Professor Shivakumar during the Spring '11 term at IIT Kanpur.

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cs2100-8-Sequential-Logic - CS2100Computer Organisation...

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