cs2100-15-Control

cs2100-15-Control - CS2100 Computer Organisation

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Unformatted text preview: CS2100 Computer Organisation http://www.comp.nus.edu.sg/~cs2100/ The Processor: Control (AY2009/2010) Semester 2 Ack: These slides are taken from Dr Tulika Mitras CS1104 notes. CS2100 Control 2 THE PROCESSOR: CONTROL ALUcontrol signals Design of ALU Control Unit Control Signals PCSrc RegDst ALUSrc MemtoReg MemRead MemWrite RegWrite CS2100 Control 3 TODAYS FOCUS Computer Processor Control Datapath Memory Devices Input Output Control CS2100 Control 4 DATAPATH VERSUS CONTROL Datapath: The collection of different elements that together provide a conduit for the flow and transformation of data in the processor during execution Control: Tells the datapath, memory, and I/O devices what to do according to the wishes of the instructions of the program Lets identify all control signals first! Control signals will be generated from machine language instructions Get ready with paper and pencil; we will do in-class exercises CS2100 Control 5 REVIEW: DATAPATH Sign extend ALU result ALU ALUcontrol 4 Zero Read register 1 Read register 2 Write register Write data Read data 1 Read data 2 RegWrite Registers Data Memory Address Read Data Write Data MemRead MemWrite 16 32 M U X M U X ALUSrc MemtoReg Add PC 4 Read address Instruction Instruction memory Add Shift left 2 M U X PCSrc Blue lines are control signals. Are there any more control signals? CS2100 Control 6 REVIEW: MIPS INSTRUCTION SUBSET 32 34 36 37 42 rs rt rd rs rt rd rs rt rd rs rt rd rs rt rd add sub and or slt opcode shamt funct R-type 31 25 20 15 10 5 35 43 4 rs rt rs rt rs rt offset offset offset lw sw beq I-type 31 25 20 15 CS2100 Control 7 REVIEW: INSTRUCTION FORMAT Opcode field (Op[5:0]) is always in bits 31:26 Two registers to be read are always specified through rs and rt fields at positions 25:21 and 20:16 for R-type instructions, branch equal, and for store instruction 16-bit offset field for branch equal, load, store is always in positions 15:0 Problem with destination register: 20:16 (rt) for load while 15:11 (rd) for R-type instructions use MUX 6 11 16 21 26 31 op rs rt rd shamt funct 6 bits 6 bits 5 bits 5 bits 5 bits 5 bits op rs rt immediate 16 21 26 31 6 bits 16 bits 5 bits 5 bits R-type I-type CS2100 Control 8 DATAPATH WITH OPERANDS DECODING Sign extend ALU result ALU ALUcontrol 4 Zero Read register 1 Read register 2 Write...
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cs2100-15-Control - CS2100 Computer Organisation

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