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cs2100-16-Pipelining

# cs2100-16-Pipelining - CS2100Computer Organisation...

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CS2100 Computer  Organisation http://www.comp.nus.edu.sg/~cs2100/ Pipelining (AY2009/2010) Semester 2

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CS2100 Pipelining 2 PIPELINING MIPS Pipeline Stages Pipelined Datapath Pipelined Execution Pipeline Control Pipelined Datapath with Control Pipeline Hazards Structural Data Control Forwarding Branch prediction
CS2100 Pipelining 3 ASSEMBLY LINE Henry Ford invented an assembly line (pipeline flow) for greater efficiency in 1913

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CS2100 Pipelining 4 LAUNDRY EXAMPLE Ann, Brian, Cathy, Dave each have one load of clothes to wash, dry, and fold Washer takes 30 minutes Dryer takes 30 minutes “Folder” takes 30 minutes “Stasher” takes 30 minutes to put clothes into drawers A B C D
CS2100 Pipelining 5 SEQUENTIAL LAUNDRY Sequential laundry takes 8 hours for 4 loads Steady state: 1 load every 2 hours If they learned pipelining, how long would laundry take? 30 T a s k O r d e r B C D A Time 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 6 PM 7 8 9 10 11 12 1 2 AM

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CS2100 Pipelining 6 PIPELINED LAUNDRY Pipelined laundry takes 3.5 hours for 4 loads! Steady state: 1 load every 30 min Potential speedup = 2 hr/30 min = 4 (# stages) Time to fill pipeline takes 2 hours speedup T a s k O r d e r B C D A Time 6 PM 7 8 9 10 11 12 1 2 AM 30 30 30 30 30 30 30
CS2100 Pipelining 7 SLOW DRYER Pipelined laundry now takes 5.5 hours! Steady state: One load every 1 hr (dryer speed) Pipeline rate is limited by the slowest stage T a s k O r d e r B C D A Time 6 PM 7 8 9 10 11 12 1 2 AM 30 30 30 30 30 30 30 30 30 30 30

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CS2100 Pipelining 8 DEPENDENCY Brian is using the laundry for the first time; he wants to see the outcome of one wash + dry cycle first before putting in his clothes Pipelined laundry now takes 4 hours T a s k O r d e r B C D A Time 6 PM 7 8 9 10 11 12 1 2 AM 30 30 30 30 30 30 30 30 Dependency Stall
CS2100 Pipelining 9 PIPELINING LESSONS Pipelining doesn’t help latency of single task, it helps throughput of entire workload Multiple tasks operating simultaneously using different resources Potential speedup = Number of pipeline stages Pipeline rate limited by slowest pipeline stage Unbalanced lengths of pipeline stages reduces speedup Time to “fill” pipeline reduces speedup Stall for dependences T a s k O r d e r B C D A Time 6 PM 7 8 9 30 30 30 30 30 30 30 Time for operation in stage i = T i Overhead for pipeline T d Time without pipelining T seq  =  Σ  T i •Time with pipelining        T pipe  = max (T i ) + T d •Speedup = Number of pipeline stages if evenly  balanced and T d  = 0

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CS2100 Pipelining 10 MIPS PIPELINE STAGES (1/2) Five Execution Stages IF : Instruction Fetch ID : Instruction Decode and Register Read EX : Execute an operation or calculate an address MEM : Access an operand in data memory WB : Write back the result into a register Each execution stage takes 1 clock cycle General flow of data is from left to right Exceptions: Update of PC and write back of register file – more about this later…
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