cs2100-17-Cache-1

cs2100-17-Cache-1 - CS2100Computer Organisation Cache I...

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CS2100 Computer  Organisation http://www.comp.nus.edu.sg/~cs2100/ Cache I (AY2009/2010) Semester 2
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CS2100 Cache I 2 WHERE ARE WE NOW? Number systems and codes Boolean algebra Logic gates and circuits Simplification Combinational circuits Sequential circuits Performance Assembly language The processor: Datapath and control Pipelining Memory hierarchy: Cache Input/output Preparation Logic Design Computer organisation
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CS2100 Cache I 3 CACHE I Memory Hierarchy Locality The Cache Principle Direct-Mapped Cache Cache Structure and Circuitry Write Policy
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CS2100 Cache I 4 TODAY’S FOCUS Computer Processor Control Memory Devices Input Output Datapath Ack: Some slides here are taken from Dr Tulika Mitra’s CS1104 notes.
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CS2100 Cache I 5 DATA TRANSFER: THE BIG PICTURE Registers are in the datapath of the processor. If operands are in memory we have to load them to processor (registers), operate on them, and store them back to memory Computer Processor Control Datapath + Registers Memory Devices Input Output Load from memory Store to memory
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CS2100 Cache I 6 MEMORY TECHNOLOGY: 1950s 1948: Maurice Wilkes examining  EDSAC’s delay line memory tubes 16-tubes each storing 32 17-bit words  Maurice Wilkes: 2005 1952: IBM 2361 16KB magnetic core memory
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CS2100 Cache I 7 MEMORY TECHNOLOGY 2005:  DRAM Infineon Technologies: stores data equivalent to 640 books, 32,000 standard newspaper pages, and 1,600 still pictures or 64 hours of sound Is this latest? Try to find out from Google
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CS2100 Cache I 8 DRAM CAPACITY GROWTH 4X capacity increase almost every 3 years, i.e., 60% increase per year for 20 years Unprecedented growth in density, but we still have a problem
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CS2100 Cache I 9 PROCESSOR-DRAM PERFORMANCE GAP µProc 60%/yr. DRAM 7%/yr. 1 10 100 1000 1980 1981 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 DRAM CPU 1982 Processor-Memory Performance Gap: (grows 50% / year) Performance Time “Moore’s Law” Memory Wall: 1 GHz Processor   1 ns per clock cycle but 50 ns to go to DRAM  50 processor clock cycles per memory access!!
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CS2100 Cache I 10 FASTER MEMORY TECHNOLOGIES: SRAM   SRAM 6 transistors per memory cell    Low  density Fast access  latency of 0.5 – 5 ns   DRAM 1 transistor per memory cell    High  density Slow access  latency of 50-70ns  SRAM
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CS2100 Cache I 11 SLOW MEMORY TECHNOLOGIES:  MAGNETIC DISK Typical high-end hard disk: Average latency: 5-20 ms Capacity: 250GB
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CS2100 Cache I 12 QUALITY VERSUS QUANTITY Capacity Latency Cost/GB Register 100s Bytes  20     ps $$$$ SRAM 100s KB 0.5-5  ns $$$ DRAM 100s MB 50-70 ns $ Hard Disk 100s GB  5-20 ms Cents Ideal 1 GB       1  ns Cheap Processor Control Datapath Registers Memory (DRAM) Devices Input Output Hard Disk
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CS2100 Cache I 13 BEST OF BOTH WORLDS What we want: A BIG and FAST memory Memory system should perform like 1GB of SRAM (1ns access time) but cost like 1GB of slow memory Key concept: Use a hierarchy of memory technologies Small but fast memory near CPU Large but slow memory farther away from CPU
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CS2100 Cache I 14 MEMORY HIERARCHY Level 1 Level 2 Level n Size Speed CPU Registers SRAM SRAM DRAM Disk
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This note was uploaded on 02/27/2011 for the course CS 2100 taught by Professor Shivakumar during the Spring '11 term at IIT Kanpur.

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cs2100-17-Cache-1 - CS2100Computer Organisation Cache I...

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