ece15_10_2011_6

# ece15_10_2011_6 - Today Fan-out ECE 15A Fundamentals of...

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1 ECE 15A Fundamentals of Logic Design Lecture 10 Malgorzata Marek-Sadowska Electrical and Computer Engineering Department UCSB 2 Today Fan-out Timing behavior of circuits Waveforms to visualize what is happening Momentary change of signals at the outputs: Hazards can be a problem Glitches: incorrect circuit operation Testing combinational circuits 3 Fan-Out (CMOS) Driving Gate 5pf 5pf • CMOS output has to charge and discharge the parallel combination of all the input capacitances •Output switching time will be increased in proportion to the number of load being driven. 4 Combinational Logic Timing: Inverter Combinational logic is made from electronic circuits An input change takes time to propagate to the output The output remains unchanged for a time period equal to the contamination delay , t cd The new output value is guaranteed to be valid after a time period equal to the propagation delay , t pd A Y A Y t pd t cd 5 Combinational Logic Timing: NOR Gate A B C A B C t pd t cd The output is guaranteed to be stable with old value until the contamination delay Unknown values shown in waveforms as Xs The output is guaranteed to be stable with the new value after the propagation delay 6 Gate Delay Gate delay- time for change at input to cause change at output Rise time- time for output to transition from low to high voltage Fall time- time for output to transition from high to low voltage rise time and fall time are often different!

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2 7 Transition times 8 Propagation Delay (cont.) Propagation delay defined as: Average time needed for an input
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ece15_10_2011_6 - Today Fan-out ECE 15A Fundamentals of...

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