homework_6_ece15a_11

homework_6_ece15a_11 - hazards in each circuit. (b) (5p)...

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Homework #6 February 4, 2011 1 Homework #6 due February 23 at noon ECE 15a Winter 2011 1. (5p) Simplify the following expression and implement it with NAND gates only. Assume that both true and complement versions of the input variables are available. F(W,X,Y,Z) = WX’+WXZ+W’Y’Z’+W’XY’+WXZ’ 2. Convert the circuit shown in Figure 1 to (5p) (a) all NAND gates, (5p) (b) all NOR gates, by adding bubbles and inverters where necessary. 3. (5p) Draw the NAND logic diagram for the following expression, using a multiple-level NAND cir- cuit: F(w,x,y,z) = w(x+y+z)+xyz 4. (5p) Realize Z=bc’(a+d+eg(f’+h)) using NOR gates. Add inverters if necessary. 5. Consider the following function: F(a,b,c,d) = Σ m(1,5,6,7,8,10, 14,15) (a) (5p) Find two different minimum circuits which implement F using AND and OR gates. Identify all
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Unformatted text preview: hazards in each circuit. (b) (5p) Find an AND-OR circuit for F which has no hazards. (c) (5p) Find an OR-AND circuit which has no hazards. 6. (10p) Complete the timing diagram in Figure 3 for the circuit in Figure 2. Assume gate delays of 5ns. a c g Z b d e h Figure 1 a c b d e Figure 2 f Homework #6 February 4, 2011 2 7. (25p) Consider the circuit in Figure 4: Draw timing diagrams for the signals a,b,c,d and F after the inputs have switched at time t0 from(x,y,z,w) = (1,1,1,0) to (1,0,1,0). This circuit has a static hazard on c and a dynamic hazard on F. The numbers inside the gate symbols represent gate delays. a Figure 3 b c d e f 0 5 10 20 30 40 50 60 70 80 90 100 110 120 3 4 3 1 3 4 x y z w a b c F d Figure 4....
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homework_6_ece15a_11 - hazards in each circuit. (b) (5p)...

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