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Unformatted text preview: hazards in each circuit. (b) (5p) Find an AND-OR circuit for F which has no hazards. (c) (5p) Find an OR-AND circuit which has no hazards. 6. (10p) Complete the timing diagram in Figure 3 for the circuit in Figure 2. Assume gate delays of 5ns. a c g Z b d e h Figure 1 a c b d e Figure 2 f Homework #6 February 4, 2011 2 7. (25p) Consider the circuit in Figure 4: Draw timing diagrams for the signals a,b,c,d and F after the inputs have switched at time t0 from(x,y,z,w) = (1,1,1,0) to (1,0,1,0). This circuit has a static hazard on c and a dynamic hazard on F. The numbers inside the gate symbols represent gate delays. a Figure 3 b c d e f 0 5 10 20 30 40 50 60 70 80 90 100 110 120 3 4 3 1 3 4 x y z w a b c F d Figure 4....
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This note was uploaded on 02/26/2011 for the course ECE 15A taught by Professor M during the Winter '08 term at UCSB.
- Winter '08