homework_8_ece15a_11

# homework_8_ece15a_11 - (5,6,13,14 C(x,y,z,w)=(6,7,14,15...

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Homework #8 February 22, 2011 1 Homework #8 due March 8 at noon ECE 15a Winter 2011 (5p)1. Build the 8-to-3 priorityencoder using two 4-to-2 priority encoders and any additional gates. (5p) 2. A combinational circuit is defined by the following three Boolean functions: F1(x,y,z) = m(2,3,4,5) F2(x,y,z) = m(1,3,5,6) F3(x,y,z) = m(1,2,4,5,6) Implement the circuit using a PLA. Minimize the numer of product terms. (5p) 3. Implement F1, F2 and F3 from problem 2 using a 3-to-8 decoder and NOR gates. (5p) 4. Implement the following Boolean function using a 2-to-1 multiplexer and two 3-variable LUTs: F(A,B,C,D) = (1,3,5,7,9,11,12,13). Specify the functions realized by each LUT. (10p) 5. Implement a full adder with two 4-to-1 multiplexers. 6. A combinational circuit is defined by the following Boolean functions: A(x,y,z,w) = (4,5,12,13) B(x,y,z,w) =
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Unformatted text preview: (5,6,13,14) C(x,y,z,w)= (6,7,14,15) D(x,y,z,w)= (4,6,7,12,14,15) (5p) (a) Tabulate the truth table for an 8x4 ROM that implements these Boolean functions (10p) (b) Tabulate the PLA programming table for these functions. Minimize the number of product terms. (5p) (c) Implement this circuit using a PAL with 3 inputs, 4 outputs and 3-wide AND-OR structure. (10p) (d) Implement this circuit using CLBs of the type shown in fig. 9-33. Specify the functions realized by each function generator. 7. (5p) Implement a full adder using only 2-1 muxes. (5p) 8. An 8x1 multiplexer has inputs a,b,c connected to the selection inputs s2,s1 and s0, respectively. The data inputs I0 through I7 are as follows: I1=I2=I7=0; I3=I5=1; I0=I4=d; I6 = d’. Determine the Boolean function that the multiplexer implements....
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