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Homework #6
ECE 15a Winter 2011
1. (5p) Simplify the following expression and implement it with NAND gates only. Assume that both
true and complement versions of the input variables are available.
F(W,X,Y,Z) = WX’+WXZ+W’Y’Z’+W’XY’+WXZ’
Solution:
The Karnaugh map of this function is as follows:
W
X
\
Y
Z0
00
11
0
00
1
01
1
1
1
1
1111
1
0
Thus, F(W,X,Y,Z)=W+Y’Z’+XY’. The NAND gate implementation is shown below:
2. Convert the circuit shown in Figure 1 to
(5p) (a) all NAND gates,
(5p) (b) all NOR gates,
by adding bubbles and inverters where necessary.
Solution:
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NAND gate implementation:
(b)
Nor gate implementation
3. (5p) Draw the NAND logic diagram for the following expression, using a multiplelevel NAND
circuit: F(w,x,y,z) = w(x+y+z)+xyz.
Solution:
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The NAND diagram is shown below:
4. (5p) Realize Z=bc’(a+d+eg(f’+h)) using NOR gates. Add inverters if necessary.
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This note was uploaded on 02/26/2011 for the course ECE 15A taught by Professor M during the Winter '08 term at UCSB.
 Winter '08
 M
 Gate

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