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ENTC_219_Syllabus - 1 ENTC 219 Digital Electronics SPRING...

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1 ENTC 219 – Digital Electronics SPRING 2011 Instructor: Joseph A. Morgan, D.E., P.E. Email: [email protected] Phone: 979-575-2 7 (text and voice) Office: Fermier 111 Lab Instructor: Pankaj Bhagawat Email: [email protected] (Primary) Phone: (Secondary) This syllabus is a tentative course schedule. The policies and dates presented here are subject to change at the discretion of the instructor. Topics: Number systems (e.g., binary, 2's complement representation), Field Programmable Logic Device (schematic capture, simulation, device configuration, programming, test and verification), Basic logic gates (e.g. AND, OR, NOT, XOR, XNOR gates), Truth tables and Karnaugh maps for designing and simplifying logic circuits, Combinational logic (e.g., multiplexers, demultiplexers, encoders, decoders), Sequential logic (e.g., flip-flops and counters), and State machines Implementation of an autonomous mobile platform controller Xilinx Race of Champions Prerequisite: None Textbook: Not Required Digital Design (3rd Edition), Mano and Mano available from Amazon.com. Lab Text: Lab assignments will be provided by the Lab Instructor Grading: In this course, homework assignments, laboratory assignments, quizzes, and exams will be used for evaluation of your performance. Midterm Exam 25 % Final Exam 35 % Laboratory 15 % Project 15% Homework and Quizzes 10 % Total 100 %
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2 Exams: There will be a Midterm exam and a comprehensive Final Exam. While tentative class dates for the exams are included in the syllabus, the actual dates will be announced in class. The final exam will be comprehensive and will be given at the time specified by the university. No make-up exams will be given. Unexcused absence from an exam or quiz will result in a grade of 0. Opportunities will be provided to improve the midterm test grade by participating in EET/TET activities. These opportunities, which will be outside of normal class/lab times, will be announced in class. For those students who complete the necessary application process and compete in the Xilinx Race of Champions, the final test grade (if higher than the Midterm grade (modified as indicated above) will be used as the Midterm grade. Homework: Developing good circuit design and analysis techniques requires substantial practice. Therefore, homework problems will be assigned in class. Being able to work each homework problem is necessary to do well in the class.
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