ENTC_219_Lab_4 - Lab 4 Combinatorial Logic Devices Due Date...

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Lab 4 – Combinatorial Logic Devices Due Date: Today + 1 Week In the previous lab, the student built their first combinational logic device commonly referred to as a decoder. In the following lab sessions, the decoder and other combinational logic devices will be applied. In today’s lab experiment, the student will design, implement, and verify a 4-bit, 2:1 multiplexer. Learning to develop such a device will be greatly beneficial for the lab project. This lab requires knowledge of Karnaugh map simplification, as well as knowledge on how to create higher level devices by cascading / combining lower level devices. Objectives c Create a 4-bit, 2:1 multiplexer device. c Construct a 4 to 1 multiplexer using 2 to 1 multiplexers with enable. c Implement multiplexer circuit in LabVIEW FPGA. c Verify design on Spartan-3E Starter Board with onboard hardware. Background & Theory Combinational logic devices, or combinatorial devices, are circuits built solely from basic logic gates. These circuits are used with a specific purpose and can be represented as a truth table. This section provides a brief discussion on a few combinatorial devices commonly used in digital logic design. In the next lab session, the remaining combinatorial devices will be discussed. Decoders / Encoders In the previous lab, a device was designed with a specific purpose to convert binary codes to a code relevant for a seven-segment display. This process of translating ambiguous information into something understood by the device receiving the data is called decoding. Therefore, the resulting device is known as a decoder . Conversely, translating data into something ambiguous is called encoding and may be achieved using an encoder . Figure 1 - 3-to-8 Line Decoder with Enable
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ENTC_219_Lab_4 - Lab 4 Combinatorial Logic Devices Due Date...

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