2008SpCS61C-L14-ddg-InstructionRepII

2008SpCS61C-L14-ddg-InstructionRepII - UCB CS61C : M achine...

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CS61C L14 MIPS Instruction Representation II (1) Garcia, Spring 2008 © Click to edit Master subtitle style inst.eecs.berkeley.edu/~cs61c UCB CS61C : Machine Structures Lecture 14 MIPS Instruction Representation II 2008-02-25 Extend moore’s law? IBM wants to use “self- assembling” nanotechnology to improve their insulators, using airgaps instead of insulating material at the nanoscale. No more photolithography, which could save $50 million on Lecturer SOE Dan Garcia www.nytimes.com/2008/02/24/business/24proto.html
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CS61C L14 MIPS Instruction Representation II (2) Garcia, Spring 2008 © Review Simplifying MIPS: Define instructions to be same size as data word (one word) so that they can use the same memory (compiler can use lw and sw ). Computer actually stores programs as a series of these 32-bit numbers. MIPS Machine Language Instruction : 32 bits representing a single instruction opcode rs rt immediate opcode rs rt rd funct shamt R I
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CS61C L14 MIPS Instruction Representation II (3) Garcia, Spring 2008 © Problem 0: Unsigned # sign-extended? addiu , sltiu , sign-extends immediates to 32 bits. Thus, # is a “signed” integer. Rationale addiu so that can add w/out overflow sltiu suffers so that we can have easy HW Does this mean we’ll get wrong answers? Nope, it means assembler has to handle any unsigned immediate 215 n < 216 (I.e., with a 1 in the 15th bit and 0 s in the upper 2 bytes) as it does for numbers that are too large. I-Format Problems (0/3)
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CS61C L14 MIPS Instruction Representation II (4) Garcia, Spring 2008 © Problem: Chances are that addi , lw , sw and slti will use immediates small enough to fit in the immediate field. …but what if it’s too big? We need a way to deal with a 32-bit immediate in any I-format instruction. I-Format Problem (1/3)
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CS61C L14 MIPS Instruction Representation II (5) Garcia, Spring 2008 © Solution to Problem: Handle it in software + new instruction Don’t change the current instructions: instead, add a new instruction to help out New instruction: lui register, immediate stands for L oad U pper I mmediate takes 16-bit immediate and puts these bits in the upper half (high order half) of the register sets lower half to 0 s I-Format Problem (2/3)
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CS61C L14 MIPS Instruction Representation II (6) Garcia, Spring 2008 © Solution to Problem (continued):
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2008SpCS61C-L14-ddg-InstructionRepII - UCB CS61C : M achine...

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