2008SpCS61C-L28-ddg-pipelineI

2008SpCS61C-L28-ddg-pipelineI - CS61C L28 CPU Design :...

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Unformatted text preview: CS61C L28 CPU Design : Pipelining to Improve Performance I (1) Garcia, Spring 2008 Click to edit Master subtitle style inst.eecs.berkeley.edu/~cs61c UCB CS61C : Machine Structures Lecture 28 CPU Design : Pipelining to Improve Performance 2008-04-07 College board retires ap cs ab exam The College Board announced in an email that it was getting rid of the AB exam (the one that articulates with CS61B). The waves of this have been felt across the US in the CS teaching crowd. Lecturer SOE Dan Garcia news.slashdot.org/news08/04/06/1916242.shtml Hi to Stu Blair from Norfolk, VA! P ic tu r e 1 8 P ic tu r e 1 6 CS AB CS61C L28 CPU Design : Pipelining to Improve Performance I (2) Garcia, Spring 2008 Review: Single cycle datapath 5 steps to design a processor 1. Analyze instruction set @ datapath requirements 2. Select set of datapath components & establish clock methodology 3. Assemble datapath meeting the requirements 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. 5. Assemble the control logic Control is the hard part MIPS makes that easier Instructions same size Source registers always in same place Immediates same size, location Operations always on registers/immediates Control Datapath Memory Processor Input Output CS61C L28 CPU Design : Pipelining to Improve Performance I (3) Garcia, Spring 2008 RegDst = add + sub ALUSrc = ori + lw + sw MemtoReg = lw RegWrite = add + sub + ori + lw MemWrite = sw nPCsel = beq Jump = jump ExtOp = lw + sw ALUctr[0] = sub + beq (assume ALUctr is 0 ADD , 01: SUB , 10: OR ) ALUctr[1] = or where, rtype = ~op5 ~op4 ~op3 ~op2 ~op1 ~op0, ori = ~op5 ~op4 op3 op2 ~op1 op0 lw = op5 6 ~op4 ~op3 ~op2 op1 op0 sw = op5 6 ~op4 op3 ~op2 op1 op0 beq = ~op5 ~op4 * ~op3 op2 ~op1 n ~op0 jump = ~op5 ~op4 D ~op3 ~op2 Z op1 ~op0 add = rtype func5 ~func4 * ~func3 ~func2 ~func1 ~func0 sub = rtype func5 ~func4 ~func3 ~func2 func1 ~func0 Omigosh omigosh, do you know what this means? add sub ori l w sw beq jump RegDst ALUSrc MemtoReg RegWrite MemWrite nPCsel Jump ExtOp ALUctr[0 ]ALUctr[1 ] AND logic OR logic opcode func How We Build The Controller CS61C L28 CPU Design : Pipelining to Improve Performance I (4) Garcia, Spring 2008 lw $t0, 0($2) lw $t1, 4($2) sw $t1, 0($2) sw $t0, 4($2) High Level Language Program (e.g., C) Assembly Language Program (e.g.,MIPS) Machine Language Program (MIPS) Hardware Architecture Description (e.g., block diagrams) Compiler Assembler Machine Interpretation temp = v[k]; v[k] = v[k+1]; v[k+1] = temp; 0000 1001 1100 0110 1010 1111 0101 1000 1010 1111 0101 1000 0000 1001 1100 0110 1100 0110 1010 1111 0101 1000 0000 1001 0101 1000 0000 1001 1100 0110 1010 1111 Logic Circuit Description (Circuit Schematic Diagrams) Architecture Implementation Call home, weve made HW/SW CS61C L28 CPU Design : Pipelining to Improve Performance I (5) Garcia, Spring 2008...
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2008SpCS61C-L28-ddg-pipelineI - CS61C L28 CPU Design :...

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