2008SpCS61C-L31-ddg-cacheII

2008SpCS61C-L31-ddg-cacheII - UCB CS61C : M achine...

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CS61C L31 Caches II (1) Garcia, Spring 2008 © Click to edit Master subtitle style inst.eecs.berkeley.edu/~cs61c UCB CS61C : Machine Structures Lecture 31 – Caches II 2008-04-14 Ibm’s “racetrack memory” In this week’s Science , IBM researchers describe a new class of data storage, called racetrack memory, combining the data storage density of disk with the ruggedness and speed of flash memory (no moving parts). They store bits as magnetic fields on nanowires. They don’t have a prototype, and say Lecturer SOE Dan Garcia www.technologyreview.com/Infotech/20553/ Hi to Yi Luo from Seattle, WA !
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CS61C L31 Caches II (2) Garcia, Spring 2008 © Direct-Mapped Cache Terminology All fields are read as unsigned integers. Index specifies the cache index (or “row”/block) Tag distinguishes betw the addresses that map to the same location Offset specifies which byte within the block we want ttttttttttttttttt iiiiiiiiii oooo tag index byte to check to offset if have select within
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CS61C L31 Caches II (3) Garcia, Spring 2008 © AREA (cache size, B) = HEIGHT (# of blocks) * WIDTH (size of one block, B/block) WIDTH (size of one block, B/block) HEIGHT (# of blocks) AREA (cache size, B) 2(H+W) = 2H * 2W T ag I ndex O ffset T I O Dan’s great cache mnemonic
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CS61C L31 Caches II (4) Garcia, Spring 2008 © Caching Terminology When reading memory, 3 things can happen: cache hit: cache block is valid and contains proper address, so read desired word cache miss: nothing in cache in appropriate block, so fetch from memory cache miss, block replacement: wrong data is in cache at appropriate block, so discard it and fetch desired data from memory (cache always copy)
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CS61C L31 Caches II (5) Garcia, Spring 2008 © Ex.: 16KB of data, direct-mapped, 4 word blocks Can you work out height, width, area? Read 4 addresses 1. 0x00000014 2. 0x0000001C 3. 0x00000034 4. 0x00008014 Memory vals here: Address (hex) Value of Word Memory 00000010 00000014 00000018 0000001C a b c d ... ... 00000030 00000034 00000038 0000003C e f g h 00008010 00008014 00008018 0000801C i j k l ... ... ... ... ... ... Accessing data in a direct mapped cache
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CS61C L31 Caches II (6) Garcia, Spring 2008 © 4 Addresses: 0x00000014, 0x0000001C, 0x00000034, 0x00008014 4 Addresses divided (for convenience) into Tag , Index Byte Offset fields 000000000000000000 0000000001 0100 000000000000000000 0000000001 1100 000000000000000000 0000000011 0100 000000000000000010 0000000001 0100 Tag Index Offset Accessing data in a direct mapped cache
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CS61C L31 Caches II (7) Garcia, Spring 2008 ©
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2008SpCS61C-L31-ddg-cacheII - UCB CS61C : M achine...

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