2008SpCS61C-L32-ddg-cacheIII

2008SpCS61C-L32-ddg-cacheIII - UCB CS61C : M achine...

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CS61C L32 Caches III (1) Garcia, Spring 2008 © Click to edit Master subtitle style inst.eecs.berkeley.edu/~cs61c UCB CS61C : Machine Structures Lecture 32 – Caches III 2008-04-16 Quantum logic gates! Prem Kumar of Northwestern has created a quantum inverter (bit flipper) within an optical fiber. Most quantum demos so far have been small-scale and isolated, but this lays the foundation for networks of quantum computers Lecturer SOE Dan Garcia www.technologyreview.com/Infotech/20565/ Hi to Chin Han from U Penn!
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CS61C L32 Caches III (2) Garcia, Spring 2008 © Mechanism for transparent movement of data among levels of a storage hierarchy set of address/value bindings address index to set of candidates compare desired address with tag service hit or miss load new block and binding on miss Valid Tag 0xc-f 0x0-3 0 1 2 3 ... 1 0 d c b a 000000000000000000 0000000001 1100 address: tag index offset Review
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CS61C L32 Caches III (3) Garcia, Spring 2008 © What to do on a write hit? Write-through update the word in cache block and corresponding word in memory Write-back update word in cache block allow memory word to be “stale” e add ‘ dirty ’ bit to each block indicating that memory needs to be updated when block is replaced e OS flushes cache before I/O… Performance trade-offs?
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CS61C L32 Caches III (4) Garcia, Spring 2008 © Block Size Tradeoff (1/3) Benefits of Larger Block Size Spatial Locality: if we access a given word, we’re likely to access other nearby words soon Very applicable with Stored-Program Concept: if we execute a given instruction, it’s likely that we’ll execute the next few as well Works nicely in sequential array accesses too
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CS61C L32 Caches III (5) Garcia, Spring 2008 © Block Size Tradeoff (2/3) Drawbacks of Larger Block Size Larger block size means larger miss penalty on a miss, takes longer time to load a new block from next level If block size is too big relative to cache size, then there are too few blocks Result: miss rate goes up In general, minimize Average Memory Access Time (AMAT) = Hit Time + Miss Penalty x Miss Rate
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CS61C L32 Caches III (6) Garcia, Spring 2008 © Block Size Tradeoff (3/3) Hit Time time to find and retrieve data from current level cache Miss Penalty average time to retrieve data on a current level miss (includes the possibility of misses on successive levels of memory hierarchy) Hit Rate % of requests that are found in current level cache Miss Rate
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CS61C L32 Caches III (7) Garcia, Spring 2008 © Extreme Example: One Big Block Cache Size = 4 bytes Block Size = 4 bytes Only ONE entry (row) in the cache! If item accessed, likely accessed again soon But unlikely will be accessed again immediately! The next access will likely to be a miss again Continually loading data into the cache but discard data (force out) before use it again Nightmare for cache designer: Ping Pong Effect Cache Data Valid Bit B 0 B 1 B 3 Tag B 2
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CS61C L32 Caches III (8) Garcia, Spring 2008 © Block Size Tradeoff Conclusions Miss
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2008SpCS61C-L32-ddg-cacheIII - UCB CS61C : M achine...

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