L03-4up - CMOS Technology 1 Qualitative MOSFET model 2 CMOS...

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L03 - CMOS Technology 1 6.004 – Fal 2010 9/16/10 CMOS Technology 1. Qualitative MOSFET model 2. CMOS logic gates 3. CMOS design issues poly metal pdi f ndi f L03 - CMOS Technology 2 6.004 – Fal 2010 9/16/10 Combinational Device Wish List ! Design our system to tolerate some amount of error ! Add positive noise margins ! VTC: gain>1 & nonlinearity ! Lots of gain ! big noise margin ! Cheap, small ! Changing voltages will require us to dissipate power, but if no voltages are changing, we’d like zero power dissipation ! Want to build devices with useful functionality (what sort of operations do we want to perform?) V OL V IL V IH V OH V in V out V in V out L03 - CMOS Technology 3 6.004 – Fal 2010 9/16/10 W L MOSFETS: Gain & non-linearity gate drain source bulk Inter-layer SiO 2 insulation Polysilicon wire Doped (p-type or n-type) silicon substrate Very thin (<20Å) high-quality SiO 2 insulating layer isolates gate from channel region. Heavily doped (n-type or p-type) di f usions Channel region: electric Feld from charges on gate locally “inverts” type of substrate to create a conducting channel between source and drain. MOSFETs (metal-oxide-semiconductor ±eld-e f ect transistors) are four- terminal voltage-controlled switches. Current ²ows between the di f usion terminals if the voltage on the gate terminal is large enough to create a conducting “channel”, otherwise the mosfet is o f and the di f usion terminals are not connected. I DS " W/L L03 - CMOS Technology 4 6.004 – Fal 2010 9/16/10 FETs as switches CONDUCTION: If a channel exists, a horizontal ±eld will cause a drift current from the drain to the source. E h gate INVERSION: A su F ciently strong vertical ±eld will a ± ract enough electrons to the surface to create a conducting n- type channel between the source and drain. The gate voltage when the channel ±rst forms is called the threshold voltage -- the mosfet switch goes from “o f to “on”. E v inversion happens here The four terminals of a Field E f ect Transistor (gate, source, drain and bulk) connect to conductors that generate a complicated set of electric ±elds in the channel region which depend on the relative voltages of each terminal. p n n source drain bulk Depletion region (no carriers) forms at PN junction. Self insulating!
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L03 - CMOS Technology 5 6.004 – Fal 2010 9/16/10 FETs come in two favors The use o± both NFETs and PFETs – complimentary transistor types – is a key to CMOS (complementary MOS) logic ±amilies. p p n G D S B G S D B G S D B Connect B to GND to keep PN reverse-biased (Vp < Vn); keeps D and S insulated ±rom B Connect B to VDD to keep PN reverse- biased n n p D S G B NFET: n-type source/drain di f usions in a p-type substrate.
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L03-4up - CMOS Technology 1 Qualitative MOSFET model 2 CMOS...

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