L06 – FSMs
1
6.004 – Fal 2010
9/28/10
(Synchronous)
Finite State Machines
Lab 2 is due tonight
Great

Theory!
WARD &
HALSTEAD
NERD
KIT
6.004
Finally!
Some ENGINEERING!
L06 – FSMs
2
6.004 – Fal 2010
9/28/10
Flip Flop Timing  I
CLK
D
Q
D
Q
D
CLK
Q
<t
PD
t
PD
: maximum propagation delay, CLK
!
Q
>t
CD
t
CD
: minimum contamination delay, CLK
!
Q
>t
SETUP
t
SETUP
: setup time
guarantee that D has propagated through feedback path before master closes
>t
HOLD
t
HOLD
: hold time
guarantee master is closed and data is stable before allowing D to change
L06 – FSMs
3
6.004 – Fal 2010
9/28/10
Flip Flop Timing  II
CLK
t
1
t
1
= t
CD,reg1
+ t
CD,1
> t
HOLD,reg2
1
D
Q
D
Q
CLK
reg1
reg2
•
Questions for registerbased
designs:
!
how much time for useful work
(i.e. for combinational logic
delay)?
!
does it help to guarantee a
minimum t
CD
?
How ‘bout
designing registers so that
t
CD,reg
> t
HOLD,reg
?
!
what happens if CLK signal
doesn’t arrive at the two
registers at exactly the
same time (a phenomenon
known as “clock skew”)?
t
2
t
2
= t
PD,reg1
+ t
PD,1
< t
CLK
 t
SETUP,reg2
Q
R1
t
CD,reg1
t
CD, 1
t
PD, 1
t
PD,reg1
Q
R1
L06 – FSMs
4
6.004 – Fal 2010
9/28/10
Our New Machine
Combinational
Logic
Current
State
New
State
Input
Output
Clock
State
Registers
k
k
m
n
• Acyclic graph
• Obeys static discipline
• Can be exhaustively enumerated
by a truth table of 2
k+m
rows and
k+n output columns
•Engineered cycles
•Works only if dynamic
discipline obeyed
•Remembers k bits for
a total of 2
k
unique
combinations
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View Full DocumentL06 – FSMs
5
6.004 – Fal 2010
9/28/10
Must Respect Timing Assumptions!
Questions:
•
Constraints on T
CD
for the logic?
•
Minimum clock period?
•
Setup, Hold times for Inputs?
Combinational
Logic
Current
State
New
State
Input
Output
Clock
t
CD,L
= ?
t
PD,L
= 5ns
t
CD,R
= 1ns
t
PD,R
= 3ns
t
S,R
= 2ns
t
H,R
= 2ns
t
CD,L
> 1 ns
t
S
= t
PD,L
+ t
S,R
= 7 nS
t
H
= t
H,R
 t
CD,L
= 1 nS
We know how fast it goes… But what can it do?
t
CD,R
(1 ns) + t
CD,L
(?) > t
H,R
(2 ns)
t
CLK
> t
PD,R
+t
PD,L
+ t
S,R
> 10nS
L06 – FSMs
6
6.004 – Fal 2010
9/28/10
A simple sequential circuit…
Lets make a digital binary
Combination Lock:
Speci±cation:
• One input ( “0” or “1”)
• One output (“Unlock” signal)
• UNLOCK is 1 if and only if:
Last 4 inputs were the
“combination”: 0110
How many
registers do
I need?
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