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L07-4up - L07 - Synchronization 1 6.004 – Fal 2010...

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Unformatted text preview: L07 - Synchronization 1 6.004 – Fal 2010 9/30/10 Synchronization, Metastability and Arbitration Due tonight: Lab #2 Due Friday: Lab #1 checko ff meeting L07 - Synchronization 2 6.004 – Fal 2010 9/30/10 The Importance of being Discrete Digital Values: Problem: Distinguishing voltages representing “1” from “0” Solution: Forbidden Zone: avoid using similar voltages for “1” and “0” Digital Time: Problem: “Which transition happened first?” questions Solution: Dynamic Discipline: avoid asking such questions in close races V OL V IL V IH V OH V OUT V IN V OL V IL V IH V OH t S t H Clk Q D t CD t PD We avoid possible errors by disciplines that avoid asking the tough questions – using a forbidden zone in both voltage and time dimensions: L07 - Synchronization 3 6.004 – Fal 2010 9/30/10 If we follow these simple rules… Can we guarantee that our system will always work? With careful design we can make sure that the dynamic discipline is obeyed everywhere*... D Q D Q Out In Combinational logic D Q Out Combinational logic D Q In Clk Combinational logic D Q Combinational logic D Q Combinational logic D Q Out Combinational logic * well, almost everywhere... L07 - Synchronization 4 6.004 – Fal 2010 9/30/10 Which edge Came FIRST? The world doesn’t run on our clock! What if each bu on input is an asynchronous 0/1 level? Lock B1 U B0 0 1 0 1 To build a system with asynchronous inputs, we have to break the rules: we cannot guarantee that setup and hold time requirements are met at the inputs! So, lets use a “synchronizer” at each input: 0 1 (Unsynchronized) U(t) (Synchronized) S(t) Clock Synchronizer Valid except for brief periods following active clock edges But what About the Dynamic Discipline? L07 - Synchronization 5 6.004 – Fal 2010 9/30/10 The Asynchronous Arbiter: a classic problem Arbiter B C S B: C: a t t B a t t C B: C: S: t D t D > t E > t E t D Arbiter specifications: • finite t D (decision time) • finite t E (allowable error) • value of S at time t C +t D : 1 if t B < t C – t E if t B > t C + t E 0, 1 otherwise CASE 1 CASE 2 CASE 3 UNSOLVABLE For NO finite value of t E and t D is this spec realizable, even with reliable components! L07 - Synchronization 6 6.004 – Fal 2010 9/30/10 Violating the Forbidden Zone t B- t C Arbiter Output 1 o ( t B = t C ) B Earlier C Earlier Arbiter B C S B: C: a t t B a t t C Issue: Mapping the continuous variable (t B – t C ) onto the discrete variable S in bounded time . With no “forbidden zone,” all inputs have to be mapped to a valid output. As the input approaches discontinuities in the mapping, it takes longer to determine the answer. Given a particular time bound, you can find an input that won’t be mapped to a valid output within the allo ed time....
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L07-4up - L07 - Synchronization 1 6.004 – Fal 2010...

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