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Unformatted text preview: L09 – Design Tradeo ff s 1 6.004 – Fal 2010 10/7/10 Design Tradeoffs Door #1: Performance Door #2: Size Door #3: Power Quiz 2 (next week) will cover materials thru today’s lecture. Lab 3 is due tonight. L09 – Design Tradeo ff s 2 6.004 – Fal 2010 10/7/10 There are a large number of implementations of the same functionality -- each represents a di ff erent point in the area- time-power space Optimization metrics: area time power 1. Area of the design 2. Throughput 3. Latency 4. Power consumption 5. Energy of executing a task 6. … Optimizing Your Design L09 – Design Tradeo ff s 3 6.004 – Fal 2010 10/7/10 t PD of Ripple-Carry Adder Worse-case path: carry propagation from LSB to MSB, e.g., when adding 11…111 to 00…001. t PD = (N-1)*(t PD,OR + t PD,AND ) + t PD,XOR ! " (N) CI to CO CI N-1 to S N-1 " (N) is read “order N” and tells us that the latency of our adder grows in proportion to the number of bits in the operands. A B CO CI S FA A B CO CI S FA A B CO CI S FA A n-1 B n-1 A n-2 B n-2 A 2 B 2 A 1 B 1 A B 0 S n-1 S n-2 S 2 S 1 S 0 A B CO CI S FA A B CO CI S FA C … CI A B S CO L09 – Design Tradeo ff s 4 6.004 – Fal 2010 10/7/10 Performance/Cost Analysis Example: n 2 # ( n 2 +2n+3) # 2 n 2 "almost always" n 2 +2n+3 = " ( n 2 ) since " (...) implies both inequalities; O(...) implies only the second. g(n) = O(f(n)) "Order Of" notation: such that for all but finitely many integral n $ 0 c 1 • f ( n ) # g ( n ) # c 2 • f ( n ) g(n) = " (f(n)) if there exist C 2 $ C 1 > , "g(n) is of order f(n)" g(n) = " (f(n)) L09 – Design Tradeo ff s 5 6.004 – Fal 2010 10/7/10 Faster Carry Logic Let’s see if we can improve the speed by rewriting the equations for C OUT : C OUT = AB + AC IN + BC IN = AB + (A + B)C IN = G + P C IN where G = AB and P = A + B generate propagate For adding two N-bit numbers, carry-in to bit N is: C N = G N-1 + P N-1 C N-1 = G N-1 + P N-1 G N-2 + P N-1 P N-2 C N-2 = G N-1 + P N-1 G N-2 + P N-1 P N-2 G N-3 + … + P N-1 ...P C IN Actually, P is usually defined as P = A & B which won’t change C OUT but will allow us to express S as a simple function of P and C IN : S = P & C IN C N in only 3 (!) gate delays: 1 for P/G generation, 1 for ANDs, 1 for final OR CI A B S CO G P L09 – Design Tradeo ff s 6 6.004 – Fal 2010 10/7/10 N-bit Addition in Constant Time? So if we had (N+1)-input gates and didn’t mind a lot of loading on the P signals , the propagation delay of adder built using P/G equation to compute C IN of each bit would be: 4 gate delays ! " (1) Of course, this is impractical when N is “large” (i.e. > 4) but it does lead to some interesting ideas: ! faster ripple-carry implementations (carry-skip, carry-select) ! hierarchical carry-lookahead adders L09 – Design Tradeo ff s 7 6.004 – Fal 2010 10/7/10 Carry-Lookahead Adders (CLA) We can build a hierarchical carry chain by generalizing our definition of the Carry Generate/Propagate (GP) Logic. We start by dividing our addend into two parts, a higher part, H, and a lower part, L. The GP function can be into two parts, a higher part, H, and a lower part, L....
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- Trigraph, Konrad Zuse, Pallavolo Modena, design tradeoffs, GP PL